參數(shù)資料
型號： ADUC7032BSTZ-88-RL
廠商： Analog Devices Inc
文件頁數(shù)： 69/120頁
文件大小： 0K
描述： IC MCU 96K FLASH DUAL 48LQFP
標(biāo)準(zhǔn)包裝： 2,000
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 20.48MHz
連通性： LIN，SPI，UART/USART
外圍設(shè)備： POR，PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 9
程序存儲器容量： 96KB（48K x 16）
程序存儲器類型： 閃存
RAM 容量： 1.5K x 32
電壓 - 電源 (Vcc/Vdd)： 3.5 V ~ 18 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 2x16b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 48-LQFP
包裝： 帶卷 (TR)
ADuC7032-8L
Rev. A | Page 52 of 120
Current Channel ADC Data Register
Name:
ADC0DAT
Address:
0xFFFF0520
Default Value:
0x0000
Access:
Read only
Function:
This current channel ADC data MMR holds the
16-bit conversion result from the I-ADC. The ADC does not
update this MMR if the ADC conversion result-ready bit
(ADCSTA[0]) is set. A read of this MMR by the MCU clears
all asserted ready flags (ADCSTA[2:0]).
Voltage Channel Data Register
Name:
ADC1DAT
Address:
0xFFFF0524
Default Value:
0x0000
Access:
Read only
Function:
This V-ADC data MMR holds the 16-bit conversion
result from the V-ADC. The ADC does not update this MMR
if the voltage conversion result-ready bit (ADCSTA[1]) is set. If
I-ADC is not active, a read of this MMR by the MCU clears all
asserted ready flags (ADCSTA[2:1]).
Temperature Channel ADC Data Register
Name:
ADC2DAT
Address:
0xFFFF0528
Default Value:
0x0000
Access:
Read only
Function:
This T-ADC data MMR holds the 16-bit conversion
result from the T-ADC. The ADC does not update this MMR
if the temperature conversion result-ready bit (ADCSTA[2]) is
set. A read of this MMR clears ADCSTA[2].
ADC FIFO Register
Name:
ADCFIFO
Address:
0xFFFF052C
Default Value:
0x0000
Access:
Read only
Function:
This 32-bit, read-only register returns the value of
the I-ADC and V-ADC conversion result held in the FIFO location
currently pointed to by the FIFO read pointer. The low 16 bits
[15:0] of this 32-bit word are the I-ADC result, and the high
16 bits [31:16] are the V-ADC result. The FIFO function is enabled
via the ADCCFG[1] bit, and three flags available in the ADCSTA
register allow user code to monitor and read the FIFO contents.
Current Channel ADC Offset Calibration Register
Name:
ADC0OF
Address:
0xFFFF0530
Default Value:
Part-specific, factory programmed
Access:
Read/write
Function:
This ADC offset MMR holds a 16-bit offset calibra-
tion coefficient for the I-ADC. The register is configured at
power-on with a factory default value. However, this register is
automatically overwritten if an offset calibration of the I-ADC is
initiated by the user via bits in the ADCMDE MMR. User code
can write to this calibration register only if the ADC is in idle
mode. An ADC must be enabled and in idle mode before being
written to any offset or gain register. The ADC must be in idle
mode for at least 23 μs.
Voltage Channel ADC Offset Calibration Register
Name:
ADC1OF
Address:
0xFFFF0534
Default Value:
Part-specific, factory programmed
Access:
Read/write
Function:
This V-ADC offset MMR holds a 16-bit offset
calibration coefficient for the voltage channel. The register is
configured at power-on with a factory default value. However,
this register is automatically overwritten if an offset calibration
of the voltage channel is initiated by the user via bits in the
ADCMDE MMR. User code can write to this calibration
register only if the ADC is in idle mode. An ADC must be
enabled and in idle mode before being written to any offset or
gain register. The ADC must be in idle mode for at least 23 μs.
Temperature Channel ADC Offset Calibration Register
Name:
ADC2OF
Address:
0xFFFF0538
Default Value:
Part-specific, factory programmed
Access:
Read/write
Function:
This T-ADC offset MMR holds a 16-bit offset cali-
bration coefficient for the temperature channel. The register is
configured at power-on with a factory default value. However,
this register is automatically overwritten if an offset calibration of
the temperature channel is initiated by the user via bits in the
ADCMDE MMR. User code can write to this calibration register
only if the ADC is in idle mode. An ADC must be enabled and in
idle mode before writing to any offset or gain register. The ADC
must be in idle mode for at least 23 μs.
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