參數(shù)資料
型號： ADUC7032BSTZ-88-RL
廠商： Analog Devices Inc
文件頁數(shù)： 30/120頁
文件大?。?/td> 0K
描述： IC MCU 96K FLASH DUAL 48LQFP
標準包裝： 2,000
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 20.48MHz
連通性： LIN，SPI，UART/USART
外圍設備： POR，PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 9
程序存儲器容量： 96KB（48K x 16）
程序存儲器類型： 閃存
RAM 容量： 1.5K x 32
電壓 - 電源 (Vcc/Vdd)： 3.5 V ~ 18 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 2x16b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 48-LQFP
包裝： 帶卷 (TR)
ADuC7032-8L
Rev. A | Page 17 of 120
Pin No.
Mnemonic
Type1
Description
6
TCK
I
JTAG Test Clock. This clock input pin is one of the standard 5-pin JTAG debug ports on the part.
It is an input pin only, and it has an internal, weak, pull-up resistor. When not in use, this pin
remains unconnected.
7
TDI
I
JTAG Test Data Input. This data input pin is one of the standard 5-pin JTAG debug ports on the
part. It is an input pin only, and it has an internal, weak, pull-up resistor. When not in use, this pin
remains unconnected.
8, 34, 35
DGND
S
Ground Reference for On-Chip Digital Circuits.
9, 16, 17,
23, 25, 26,
32, 38, 39,
40, 43, 45
NC
No Connect. This pin is not connected internally but is reserved for possible future use. Therefore,
this pin should not be connected externally. NC pins can be grounded, if required.
10
TDO
O
JTAG Test Data Output. This data output pin is one of the standard 5-pin JTAG debug ports on
the part. It is an output pin only. At power-on, this output is disabled and pulled high via an
internal, weak, pull-up resistor. When not in use, this pin remains unconnected.
11
NTRST
I
JTAG Test Reset. This reset input pin is one of the standard 5-pin JTAG debug ports on the part.
It is an input pin only, and it has an internal, weak, pull-down resistor. When not in use, this pin
remains unconnected. It is also monitored by the on-chip kernel to enable LIN boot load mode.
12
TMS
I
JTAG Test Mode Select. This mode select input pin is one of the standard 5-pin JTAG debug ports
on the part. It is an input pin only, and it has an internal, weak, pull-up resistor. When not in use,
this pin remains unconnected.
13
VBAT
I
Battery Voltage Input to Resistor Divider.
14
VREF
I
External Reference Input Terminal. If this input is not used, connect it directly to the AGND
system ground.
15
GND_SW
S
Switch to Internal Analog Ground Reference. Negative input for external temperature channel
and external reference. If this input is not used, connect it directly to the AGND system ground.
18
VTEMP
I
External Pin for NTC/PTC Temperature Measurement.
19
IIN+
I
Positive Differential Input for Current Channel.
20
IIN
I
Negative Differential Input for Current Channel.
21, 22
AGND
S
Ground Reference for On-Chip Precision Analog Circuits.
24
REG_AVDD
S
Nominal 2.6 V Output from On-Chip Regulator.
27
GPIO_0/IRQ0/SS
I/O
General-Purpose Digital I/O 0, External Interrupt Request 0, or SPI Interface. By default and after
power-on reset, this pin is configured as an input. The pin has an internal, weak, pull-up resistor
and, when not in use, it remains unconnected. This multifunction pin can be configured in one
of three states, namely
General-Purpose Digital I/O 0.
External Interrupt Request 0, active high.
SPI interface, slave select input.
28
GPIO_1/SCLK
I/O
General-Purpose Digital I/O 1 or SPI Interface. By default and after power-on reset, this pin is
configured as an input. The pin has an internal, weak, pull-up resistor and, when not in use, it
remains unconnected. This multifunction pin can be configured in one of two states, namely
General-Purpose Digital I/O 1.
SPI interface, serial clock input.
29
GPIO_2/MIS0
I/O
General-Purpose Digital I/O 2 or SPI Interface. By default and after power-on reset, this pin is
configured as an input. The pin has an internal, weak, pull-up resistor and, when not in use, it
remains unconnected.This multifunction pin can be configured in one of two states, namely
General-Purpose Digital I/O 2.
SPI interface, master input/slave output pin.
30
GPIO_3/MOSI
I/O
General-Purpose Digital I/O 3 or SPI Interface. By default and after power-on reset, this pin is
configured as an input. The pin has an internal, weak, pull-up resistor and, when not in use, it
remains unconnected. This multifunction pin can be configured in one of two states, namely
General-Purpose Digital I/O 3.
SPI interface, master output/slave input pin.
31
GPIO_4/ECLK
I/O
General-Purpose Digital I/O 4 or Clock Output. By default and after power-on reset, this pin is
configured as an input. The pin has an internal, weak, pull-up resistor and, when not in use, it
remains unconnected. This programmable digital I/O pin can also be configured to output
a 2.56 MHz clock.
33
REG_DVDD
S
Nominal 2.6 V Output from the On-Chip Regulator.
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