參數(shù)資料
型號(hào)： ADUC7032BSTZ-88-RL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 63/120頁(yè)
文件大?。?/td> 0K
描述： IC MCU 96K FLASH DUAL 48LQFP
標(biāo)準(zhǔn)包裝： 2,000
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 20.48MHz
連通性： LIN，SPI，UART/USART
外圍設(shè)備： POR，PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 9
程序存儲(chǔ)器容量： 96KB（48K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 1.5K x 32
電壓 - 電源 (Vcc/Vdd)： 3.5 V ~ 18 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 2x16b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 48-LQFP
包裝： 帶卷 (TR)
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ADuC7032-8L
Rev. A | Page 47 of 120
Voltage Channel ADC Control Register
Name:
ADC1CON
Address:
0xFFFF0510
Default Value:
0x0000
Access:
Read/write
Function:
The voltage channel ADC control MMR is a 16-bit register that is used to configure the V-ADC. Note that when enabling/
disabling the voltage ADC, the voltage attenuator must also be enabled/disabled via HVCFG1[7].
Table 38. ADC1CON MMR Bit Designations
Bit
Description
15
Voltage Channel ADC Enable .
Set to 1 by user code to enable the V-ADC. When enabling/disabling the voltage ADC, the voltage attenuator must also be
enabled/disabled via HVCFG1[7].
Cleared to 0 to power down the V-ADC.
14 to 10
Not Used. Reserved for future functionality and should not be modified by user code.
9
Voltage Channel ADC Output Coding.
Set to 1 by user code to configure V-ADC output coding as unipolar.
Cleared to 0 by user code to configure V-ADC output coding as twos complement.
8
Not Used. This bit is reserved for future functionality and should be written as 0 by user code.
7 to 6
Voltage Channel ADC Input Select.
00 = VBAT/24, AGND; VBAT attenuator selected.
01 = not defined.
10 = not defined.
11 = internal short; shorted input.
5 to 4
Voltage Channel ADC Reference Select.
00 = internal, 1.2 V precision reference selected.
01 = external reference inputs (VREF, GND_SW) selected.
10 = external reference inputs divided by 2 ((VREF, GND_SW)/2) selected. This allows an external reference up to REG_AVDD.
11 = (REG_AVDD, AGND) divided by 2 selected.
3 to 0
Not Used. Reserved for future functionality and should be written as 0 by user code.
Temperature Channel ADC Control Register
Name:
ADC2CON
Address:
0xFFFF0514
Default Value:
0x0000
Access:
Read/write
Function:
The temperature channel ADC control MMR is a 16-bit register that is used to configure the T-ADC.
Table 39. ADC2CON MMR Bit Designations
Bit
Description
15
Temperature Channel ADC Enable.
Set to 1 by user code to enable the T-ADC.
Cleared to 0 to power down the T-ADC.
14 to 13
VTEMP Current Source Enable.
00 = current sources off.
01 = enable 50 μA current source on VTEMP.
10 = enable 50 μA current source on GND_SW.
11 = enable 50 μA current source on both VTEMP and GND_SW.
Note that these current sources have a tolerance of ±30%.
12 to 10
Not Used. Reserved for future functionality and should not be modified by user code.
9
Temperature Channel ADC Output Coding.
Set to 1 by user code to configure T-ADC output coding as unipolar.
Cleared to 0 by user code to configure T-ADC output coding as twos complement.
8
Not Used. Reserved for future functionality and should be written as 0 by user code.
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