參數(shù)資料
型號： ADUC7032BSTZ-88-RL
廠商： Analog Devices Inc
文件頁數(shù)： 119/120頁
文件大?。?/td> 0K
描述： IC MCU 96K FLASH DUAL 48LQFP
標(biāo)準(zhǔn)包裝： 2,000
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 20.48MHz
連通性： LIN，SPI，UART/USART
外圍設(shè)備： POR，PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 9
程序存儲器容量： 96KB（48K x 16）
程序存儲器類型： 閃存
RAM 容量： 1.5K x 32
電壓 - 電源 (Vcc/Vdd)： 3.5 V ~ 18 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 2x16b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 48-LQFP
包裝： 帶卷 (TR)
ADuC7032-8L
Rev. A | Page 98 of 120
UART TX Register
Name:
COMTX
Address:
0xFFFF0700
Default Value:
0x00
Access:
Write only
Function:
This 8-bit register is written to when transmitting
data using the UART.
UART RX Register
Name:
COMRX
Address:
0xFFFF0700
Default Value:
0x00
Access:
Read only
Function:
This 8-bit register is read from to receive data
transmitted using the UART.
UART Divisor Latch Register 0
Name:
COMDIV0
Address:
0xFFFF0700
Default Value:
0x00
Access:
Read/write
Function:
This 8-bit register contains the least significant byte
of the divisor latch that controls the baud rate at which the
UART operates.
UART Divisor Latch Register 1
Name:
COMDIV1
Address:
0xFFFF0704
Default Value:
0x00
Access:
Read/write
Function:
This 8-bit register contains the most significant byte of
the divisor latch that controls the baud rate at which the UART
operates.
UART Control Register 0
Name:
COMCON0
Address:
0xFFFF070C
Default Value:
0x00
Access:
Read/write
Function:
This 8-bit register controls the operation of the UART in conjunction with COMCON1.
Table 81. COMCON0 MMR Bit Designations
Bit
Name
Description
7
DLAB
Divisor Latch Access.
Set by user to enable access to COMDIV0 and COMDIV1 registers.
Cleared by user to disable access to COMDIV0 and COMDIV1 and enable access to COMRX, COMTX, and COMIEN0.
6
BRK
Set Break.
Set by user to force TxD to 0.
Cleared to operate in normal mode.
5
SP
Stick Parity. Set by user to force parity to defined values.
1 if EPS = 1 and PEN = 1.
0 if EPS = 0 and PEN = 1.
4
EPS
Even Parity Select Bit.
Set for even parity.
Cleared for odd parity.
3
PEN
Parity Enable Bit.
Set by user to transmit and check the parity bit.
Cleared by user for no parity transmission or checking.
2
STOP
Stop Bit.
Set by user to transmit 1.5 stops bit if the word length is five bits or two stop bits if the word length is six, seven, or
eight bits. The receiver checks the first stop bit only, regardless of the number of stop bits selected.
Cleared by user to generate one STOP bit in the transmitted data.
1 to 0
WLS
Word Length Select.
00 = 5 bits.
01 = 6 bits.
10 = 7 bits.
11 = 8 bits.
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