參數(shù)資料
型號(hào)： ADUC7032BSTZ-88-RL
廠商： Analog Devices Inc
文件頁數(shù)： 68/120頁
文件大?。?/td> 0K
描述： IC MCU 96K FLASH DUAL 48LQFP
標(biāo)準(zhǔn)包裝： 2,000
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 20.48MHz
連通性： LIN，SPI，UART/USART
外圍設(shè)備： POR，PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 9
程序存儲(chǔ)器容量： 96KB（48K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 1.5K x 32
電壓 - 電源 (Vcc/Vdd)： 3.5 V ~ 18 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 2x16b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 48-LQFP
包裝： 帶卷 (TR)
ADuC7032-8L
Rev. A | Page 51 of 120
ADC Configuration Register
Name:
ADCCFG
Address:
0xFFFF051C
Default Value:
0x00
Access:
Read/write
Function:
The 8-bit ADC configuration MMR controls extended functionality related to the on-chip ADCs.
Table 43. ADCCFG MMR Bit Designations
Bit
Description
7
Analog Ground Switch Enable.
Set to 1 by user software to connect the external GND_SW pin (Pin 15) to an internal analog ground reference point. This bit
can be used to connect and disconnect external circuits and components to ground under program control and thereby
minimize dc current consumption when the external circuit or component is not being used. This bit is used in conjunction
with ADCMDE[6] to select a 20 kΩ resistor to ground.
6 to 5
Current Channel (32-Bit) Accumulator Enable.
00 = accumulator disabled and reset to 0. The accumulator must be disabled for a full ADC conversion, (ADCSTA[0] set twice)
before the accumulator can be re-enabled to ensure the accumulator is reset.
01 = accumulator active.
Positive current values are added to the accumulator total. The accumulator can overflow if allowed to run for >65,535 conversions.
Negative current values are subtracted from the accumulator total. The accumulator is clamped to a minimum value of 0.
10 = accumulator active.
Positive current values are added to the accumulator total. The accumulator can overflow if allowed to run for >65,535 conversions.
The absolute values of negative current are subtracted from the accumulator total. In this mode, the accumulator continues
to accumulate negatively, below 0.
11 = accumulator and accumulator comparator enabled. This mode is the same as Mode 10 but with the accumulator
comparator enabled.
4 to 3
Current Channel ADC Comparator Enable.
00 = comparator disabled.
01 = comparator active, interrupt asserted if absolute value of I-ADC conversion result |I| ≥ ADC0TH.
10 = comparator-count mode active, interrupt asserted if the absolute value of an I-ADC conversion result |I| ≥ ADC0TH for
number of ADC0TCL conversions; conversion value |I| < ADC0TH resets the threshold counter value (ADC0THV) to 0.
11 = comparator-count mode active, interrupt asserted if absolute value of an I-ADC conversion result |I| ≥ ADC0TH for
number of ADC0TCL conversions; conversion value |I| < ADC0TH decrements the threshold counter value (ADC0THV) towards 0.
2
Current Channel ADC Overrange Enable.
Set by user to enable a coarse comparator on the current channel ADC. If the current reading is grossly (>30% approximate)
overranged for the active gain setting, then the overrange bit in the ADCSTA MMR is set. For the flag to be set, the current
must be outside this range for >125 μs. This feature should not be used in ADC low power mode.
1
ADC FIFO Enable.
Set to 1 by user code to enable ADC FIFO on current and voltage ADC channels. The FIFO function allows up to 32 current
and voltage ADC results to be stored in an on-chip FIFO. The current status of the FIFO is reflected by three bits in the ADCSTA
register. If more than 32 results are stored in the FIFO, the contents of the FIFO may be corrupted.
0
Current Channel ADC, Result Counter Enable.
Set by user to enable the result count mode. In this mode, an I-ADC interrupt is generated only when ADC0RCV =
ADC0RCL. This allows the I-ADC to continuously monitor current but interrupt the MCU core only after a defined
number of conversions. Note that unless the ADC FIFO is enabled (ADCCNG[1] = 1), only the last conversion value is
available (intermediate I-ADC conversion results are not stored) when the ADC counter interrupt occurs. The voltage
and temperature ADCs also continue to convert if enabled, but again, only the last conversion result is available
(intermediate V-ADC and T-ADC conversion results are not stored) when the ADC counter interrupt occurs.
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