參數(shù)資料
型號(hào): ADUC7032BSTZ-88-RL
廠商: Analog Devices Inc
文件頁數(shù): 116/120頁
文件大?。?/td> 0K
描述: IC MCU 96K FLASH DUAL 48LQFP
標(biāo)準(zhǔn)包裝: 2,000
系列: MicroConverter® ADuC7xxx
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 20.48MHz
連通性: LIN,SPI,UART/USART
外圍設(shè)備: POR,PSM,溫度傳感器,WDT
輸入/輸出數(shù): 9
程序存儲(chǔ)器容量: 96KB(48K x 16)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 1.5K x 32
電壓 - 電源 (Vcc/Vdd): 3.5 V ~ 18 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 2x16b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 48-LQFP
包裝: 帶卷 (TR)
ADuC7032-8L
Rev. A | Page 95 of 120
WU (WAKE-UP) PIN
The WU (wake-up) pin is a high voltage GPIO controlled via
HVCON and HVDAT.
WU Pin Circuit Description
The WU pin is configured by default as an output with an
internal 10 kΩ pull-down resistor and high-side FET driver.
The WU pin, in its default mode of operation, is specified to
generate an active high system wake-up request by forcing the
external system WU bus high. User code can assert the WU
output by writing directly to HVCFG0[4].
It should be noted that the output responds only after the 10 μs
latency through the (serial communication based) high voltage
interface.
The internal FET is capable of sourcing significant current and,
therefore, a substantial on-chip self-heating can occur if this
driver is asserted for a long time period. For this reason,
a monoflop (a 1.3-second timeout timer) has been included.
By default, the monoflop is enabled and disables the WU driver
after 1.3 seconds. It is possible to disable the monoflop via
HVCFG1[1]. If the WU monoflop is disabled, then the WU
driver should be disabled after 1.3 seconds.
The WU pin also features a short-circuit detection feature.
When the WU pin sources more than 200 mA for 400 μs,
a high voltage interrupt is generated with HVMON[0] set.
By default, a thermal shutdown event disables the WU driver.
The WU driver must be re-enabled manually after a thermal
event via HVCFG1[3]. It is possible to disable the automatic
shutdown during a thermal event via HVCFG0[7].
The WU pin can be configured in I/O mode by writing a 1 to
HVCFG1[4]. In this mode, a rising or falling edge immediately
generates a high voltage interrupt. HVMON[7] directly reflects
the state of the external WU pin. This comparator has a trip
level of 3 V typical.
VDD
INTERNAL
SENSE
RESISTOR
SHORT-CIRCUIT
TRIP REFERENCE
SHORT-CIRCUIT
PROTECTION
OUTPUT CONTROL
HVMON[0]
NORMAL
HVCFG0[4]
NORMAL
HVMON[7]
400s
GLITCH
IMMUNITY
3V
ENABLE
READBACK
HVCFG1[4]
INTERNAL
10k
RESISTOR
IO_VSS
6k
OPEN-CIRCUIT
DIAGNOSTIC
RESISTOR
EXTERNAL
WU PIN
EXTERNAL
WAKE BUS
CLOAD
91nF
RLOAD
1k
EXTERNAL
CURRENT-LIMIT
RESISTOR
39
HVCFG1[0]
05
98
6-
0
46
Figure 38. WU Circuit, Block Diagram
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