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| 型號(hào)： | PSOC |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 8-Bit Programmable System-on-Chip (PSoC⑩) Microcontrollers |
| 中文描述： | 8位可編程系統(tǒng)（的PSoC⑩）微控制器片上 |
| 文件頁數(shù)： | 99/148頁 |
| 文件大?。?/td> | 1412K |
| 代理商： | PSOC |
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Analog PSoC Blocks
September 5, 2002
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
99
10.11 Analog Comparator Bus
Each analog column has a dedicated comparator bus
associated with it. Every analog PSoC block has a com-
parator output that can drive out on this bus, but the
comparator output from only one analog block in a col-
umn can be actively driving the comparator bus for that
column at any one time. The output on the comparator
bus can drive into the digital blocks, and is also available
to be read in the Analog Comparator Control Register
(CMP_CR, Address = Bank 0,64H).
The comparator bus is latched before it is available to
either drive the digital blocks, or be read in the Analog
Comparator Control Register. The latch for each compar-
ator bus is transparent (the output tracks the input) dur-
ing the high period of PHI2. During the low period of
PHI2 the latch retains the value on the comparator bus
during the high to low transition of PHI2.
The output from the analog block that is actively driving
the bus may also be latched internal to the analog block
itself.
In the Continuous Time analog blocks, the CPhase and
CLatch bits inside the Analog Continuous Time Type A
Block xx Control Register 2 determine whether the out-
put signal on the comparator bus is latched inside the
block, and if it is, which clock phase it is latched on.
In the Switched Capacitor analog blocks, the output on
the comparator bus is always latched. The ClockPhase
bit in the Analog SwitchCap Type A Block xx Control
Register 0 or the Analog SwitchCap Type B Block xx
Control Register 0 determines the phase on which this
data is latched and available.
Analog Comparator Control Register (CMP_CR, Address = Bank 0, 64h)
10.12 Analog Synchronization
For high precision analog operation, it may be necessary
to precisely time when updated register values are avail-
able to the analog PSOC blocks. The optimum time to
update values in Switch Cap registers is at the beginning
of the PHI1 active period. The SYNCEN bit in the Analog
Synchronization Control Register is designed to address
this. (The AINT bits of the Analog Comparator Register
(CMP_CR) are another way to address it with interrupts.)
When the SYNCEN bit is set, a subsequent write instruc-
tion to any register in a Switch Cap block will cause the
CPU to stall until the rising edge of PHI1. This mode is in
effect until the SYNCEN bit is cleared.
Table 76:
Analog Comparator Control Register
Bit #
POR
Read/
Write
Bit Name
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R
R
R
R
RW
RW
RW
RW
COMP 3
COMP 2
COMP 1
COMP 0
AINT 3
AINT 2
AINT 1
AINT 0
Bit 7: COMP 3 COMP 3 bit [0] indicates the state of the analog comparator bus for the Analog Column x
Bit 6: COMP 2 COMP 2 bit [0] indicates the state of the analog comparator bus for the Analog Column x
Bit 5: COMP 1 COMP 1 bit [0] indicates the state of the analog comparator bus for the Analog Column x
Bit 4: COMP 0 COMP 0 bit [0] indicates the state of the analog comparator bus for the Analog Column x
Bit 3: AINT 3 AINT 3 bit [0] or [1] (as defined below) selects the Analog Interrupt Source for the Analog Column x
Bit 2: AINT 2 AINT 2 bit [0] or [1] (as defined below) selects the Analog Interrupt Source for the Analog Column x
Bit 1: AINT 1 AINT 1 bit [0] or [1] (as defined below) selects the Analog Interrupt Source for the Analog Column x
Bit 0: AINT 0 AINT 0 bit [0] or [1] (as defined below) selects the Analog Interrupt Source for the Analog Column x
0 = Comparator bus
1 = PHI2 (Falling edge of PHI2 causes an interrupt)
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