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| 型號(hào)： | PSOC |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 8-Bit Programmable System-on-Chip (PSoC⑩) Microcontrollers |
| 中文描述： | 8位可編程系統(tǒng)（的PSoC⑩）微控制器片上 |
| 文件頁(yè)數(shù)： | 54/148頁(yè) |
| 文件大?。?/td> | 1412K |
| 代理商： | PSOC |
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Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet
54
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
September 5, 2002
9.3
Digital PSoC Block Bank 0 Registers
There are four user registers within each digital PSoC
block: three data registers, and one status/control regis-
ter. The three data registers are DR0, which is a shifter/
counter, and DR1 and DR2 registers, which contain data
used during the operation. The status/control register
(CR0) contains an enable bit that is used for all configu-
rations. In addition, it contains function-specific status
and control, which is outlined below.
9.3.1
Digital Basic Type A / Communications Type A Block xx Data Register 0,1,2
Digital Basic Type A Block 00 Data Register 0
Digital Basic Type A Block 00 Data Register 1
Digital Basic Type A Block 00 Data Register 2
Digital Basic Type A Block 01 Data Register 0
Digital Basic Type A Block 01 Data Register 1
Digital Basic Type A Block 01 Data Register 2
Digital Basic Type A Block 02 Data Register 0
Digital Basic Type A Block 02 Data Register 1
Digital Basic Type A Block 02 Data Register 2
Digital Basic Type A Block 03 Data Register 0
Digital Basic Type A Block 03 Data Register 1
Digital Basic Type A Block 03 Data Register 2
Digital Communications Type A Block 04 Data Register 0
Digital Communications Type A Block 04 Data Register 1
Digital Communications Type A Block 04 Data Register 2
Digital Communications Type A Block 05 Data Register 0
Digital Communications Type A Block 05 Data Register 1
Digital Communications Type A Block 05 Data Register 2
Digital Communications Type A Block 06 Data Register 0
Digital Communications Type A Block 06 Data Register 1
(DBA00DR0, Address = Bank 0, 20h)
(DBA00DR1, Address = Bank 0, 21h)
(DBA00DR2, Address = Bank 0, 22h)
(DBA01DR0, Address = Bank 0, 24h)
(DBA01DR1, Address = Bank 0, 25h)
(DBA01DR2, Address = Bank 0, 26h)
(DBA02DR0, Address = Bank 0, 28h)
(DBA02DR1, Address = Bank 0, 29h)
(DBA02DR2, Address = Bank 0, 2Ah)
(DBA03DR0, Address = Bank 0, 2Ch)
(DBA03DR1, Address = Bank 0, 2Dh)
(DBA03DR2, Address = Bank 0, 2Eh)
(DCA04DR0, Address = Bank 0, 30h)
(DCA04DR1, Address = Bank 0, 31h)
(DCA04DR2, Address = Bank 0, 32h)
(DCA05DR0, Address = Bank 0, 34h)
(DCA05DR1, Address = Bank 0, 35h)
(DCA05DR2, Address = Bank 0, 36h)
(DCA06DR0, Address = Bank 0, 38h)
(DCA06DR1, Address = Bank 0, 39h)
Table 51:
Digital Function Outputs
Function
Primary Output
Auxiliary Output
Auxiliary Input
Timer
Terminal Count
Compare True
N/A
Counter
Compare True
Terminal Count
N/A
CRC
N/A
Compare True
N/A
PRS
Serial Data
Compare True
N/A
Deadband
F0
F1
N/A
TX UART
TX Data Out
N/A
N/A
RX UART
N/A
N/A
N/A
SPI Master
MOSI
SCLK
N/A
SPI Slave
MISO
N/A
SS_
Table 52:
Digital Basic Type A / Communications Type A Block xx Data Register 0,1,2
Bit #
POR
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Read/Write
VF
1
1.
Varies by function/User Module selection. (See
Table 53 on page 55
.)
VF
1
VF
1
VF
1
VF
1
VF
1
VF
1
VF
1
Bit Name
Data [7]
Data [6]
Data [5]
Data [4]
Data [3]
Data [2]
Data [1]
Data [0]
Bit [7:0]
:
Data [7:0]
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