參數(shù)資料
型號： PSOC
廠商： Cypress Semiconductor Corp.
英文描述： 8-Bit Programmable System-on-Chip (PSoC⑩) Microcontrollers
中文描述： 8位可編程系統(tǒng)（的PSoC⑩）微控制器片上
文件頁數(shù)： 29/148頁
文件大小： 1412K
代理商： PSOC
I/O Ports
September 5, 2002
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
29
5.0
I/O Ports
5.1
Introduction
Up to five 8-bit-wide I/O ports (P0-P4) and one 4-bit wide
I/O port (P5) are implemented. The number of general
purpose I/Os implemented and connected to pins
depends on the individual part chosen. All port bits are
independently programmable and have the following
capabilities:
General-purpose digital input readable by the CPU.
General-purpose digital output writable by the CPU.
Independent control of data direction for each port
bit.
Independent access for each port bit to Global Input
and Global Output busses.
Interrupt programmable to assert on rising edge,
falling edge, or change from last pin state read.
Output drive strength programmable in logic 0 and 1
states as strong, resistive (pull-up or pull-down), or
high impedance.
Port 1, pin 0 is used in conjunction with device Test
Mode and will not function as an output for approxi-
mately 16 ms after X
RES
. After negating X
RES
, the pin
will be held low for approximately 16 ms. This does not
prevent the CPU from writing to this Data Register bit
(PRT0DR, bit 0). However, the written data will not
appear on the output pin until after the 16 ms delay.
There are no restrictions when using the pin as an input.
In addition, the pin may also be configured (e.g., drive
strength, interrupts) during this time. A device reset with
Power On Reset (POR) will not exhibit this problem
because there is a CPU hold-off time of approximately
64 ms before code execution begins.
In System Sleep State, GPIO Pins P2[4] and P2[6]
should be held to a logic low or a false Low Voltage
Detect interrupt may be triggered. The cause is in the
System Sleep State, the internal Bandgap reference
generator is turned off and the reference voltage is main-
tained on a capacitor.
The circumstances are that during sleep, the reference
voltage on the capacitor is refreshed periodically at the
sleep system duty cycle. Between refresh cycles, this
voltage may leak slightly to either the positive supply or
ground. If pins P2[4] or P2[6] are in a high state, the leak-
age to the positive supply is accelerated (especially at
high temperature). Since the reference voltage is com-
pared to the supply to detect a low voltage condition, this
accelerated leakage to the positive supply voltage will
cause that voltage to appear lower than it actually is,
leading to the generation of a false Low Voltage Detect
interrupt.
Port 0 and Port 2 have additional analog input and/or
analog output capability. The specific routing and multi-
plexing of analog signals is shown in the following dia-
gram:
相關(guān)PDF資料
PDF描述
PSOT03LC ULTRA LOW CAPACITANCE TVS ARRAY
PS0T03LC ULTRA LOW CAPACITANCE TVS ARRAY
PSOT05LC ULTRA LOW CAPACITANCE TVS ARRAY
PSOT08LC ULTRA LOW CAPACITANCE TVS ARRAY
PSOT12LC D-SUB
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSOK10001 制造商:Value Added 功能描述:
PSOODO3A 制造商:MACOM 制造商全稱:Tyco Electronics 功能描述:Versatile Power Entry Module with Small Footprint
PSOODO3B 制造商:MACOM 制造商全稱:Tyco Electronics 功能描述:Versatile Power Entry Module with Small Footprint
PSOODO6A 制造商:MACOM 制造商全稱:Tyco Electronics 功能描述:Versatile Power Entry Module with Small Footprint
PSOODO6B 制造商:MACOM 制造商全稱:Tyco Electronics 功能描述:Versatile Power Entry Module with Small Footprint
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*