參數(shù)資料
型號(hào)： PSOC
廠商： Cypress Semiconductor Corp.
英文描述： 8-Bit Programmable System-on-Chip (PSoC⑩) Microcontrollers
中文描述： 8位可編程系統(tǒng)（的PSoC⑩）微控制器片上
文件頁數(shù)： 72/148頁
文件大小： 1412K
代理商： PSOC
Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet
72
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
September 5, 2002
10.2
Analog System Clocking Signals
10.3
Array of Analog PSoC Blocks
Table 61:
Analog System Clocking Signals
Signal
Definition
ACLK0
A system-clocking signal that is driven by the clock output of a digital PSoC block and can be selected
by the user to drive the clocking signal to an analog column. Any of the 8 digital PSoC blocks can be
muxed into this line using the ACLK0[2:0] bits in the Analog Clock Select Register (CLK_CR1).
ACLK1
A system-clocking signal that is driven by the clock output of a digital PSoC block and can be selected
by the user to drive the clocking signal to an analog column. Any of the 8 digital PSoC blocks can be
muxed into this line using the ACLK1[2:0] bits in the Analog Clock Select Register (CLK_CR1).
Acolumn0
A system-clocking signal that can drive all analog PSoC blocks in Analog Column 0. This signal is
derived from the muxed input of the
24V1
,
24V2
,
ACLK0
, and
ACLK1
system clock signals. The output
of this mux is then passed through a 1:4 divider to reduce the frequency by a factor of 4. The
Acolumn0[1:0] bits in the CLK_CR0 Register determine the selected Column Clock.
Acolumn1
A system-clocking signal that can drive all analog PSoC blocks in Analog Column 1. This signal is
derived from the muxed input of the
24V1
,
24V2
,
ACLK0
, and
ACLK1
system clock signals. The output
of this mux is then passed through a 1:4 divider to reduce the frequency by a factor of 4.The
Acolumn1[1:0] bits in the CLK_CR0 Register determine the selected Column Clock.
Acolumn2
A system-clocking signal that can drive all analog PSoC blocks in Analog Column 2. This signal is
derived from the muxed input of the
24V1
,
24V2
,
ACLK0
, and
ACLK1
system clock signals. The output
of this mux is then passed through a 1:4 divider to reduce the frequency by a factor of 4. The
Acolumn2[1:0] bits in the CLK_CR0 Register determine the selected Column Clock.
Acolumn3
A system-clocking signal that can drive all analog PSoC blocks in Analog Column 3. This signal is
derived from the muxed input of the
24V1
,
24V2
,
ACLK0
, and
ACLK1
system clock signals. The output
of this mux is then passed through a 1:4 divider to reduce the frequency by a factor of 4. The
Acolumn3[1:0] bits in the CLK_CR0 Register determine the selected Column Clock.
Figure 16: Array of Analog PSoC Blocks
ACA00
ACA03
ACA02
ACA01
ASA10
ASA23
ASA12
ASA21
ASB20
ASB13
ASB22
ASB11
Analog
Column 0
Analog
Column 1
Analog
Column 3
Analog
Column 2
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