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| 型號： | PSOC |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 8-Bit Programmable System-on-Chip (PSoC⑩) Microcontrollers |
| 中文描述： | 8位可編程系統(tǒng)（的PSoC⑩）微控制器片上 |
| 文件頁數(shù)： | 62/148頁 |
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| 代理商： | PSOC |
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Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet
62
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
September 5, 2002
4.
Capture vs. Compare
A capture event will overwrite Data Register 2. This
is also the register that holds the compare value.
Therefore, using the capture function may not be
compatible with using the timer compare function.
9.5.2
Counter with Optional Compare (Pulse-
Width) Output
9.5.2.1
Summary
Conceptually, a counter measures the number of events
between “ticks,” however, this distinction between
counter and timer blurs because both functions provide a
complete range of clock selections. The counter trades
the timer’s hardware capture for a clock gate or ”enable”
and provides a means of adjusting the duty cycle of its
output so that it can double as a pulse-width modulator.
A down counter lies at the heart of the counter function.
Counter-configured PSoC blocks may be chained to
arbitrary lengths in 8 bit increments.
In a Counter User Module, the data input is an enable for
counting. Normally, when the enable goes low, the
counter will hold the current count. However, if the
enable happens to go low in the same clock period as
Terminal Count (count of all 0's), one additional count will
occur that will reload the counter from the Period Regis-
ter. Once the counter is reloaded from the Period Regis-
ter, counting will stop.
9.5.2.2
Registers
Data Register 1 establishes the period of the counter.
Data Register 0 holds the current state of the down
counter. If the function is disabled, writing a period into
Data Register 1, will automatically load Data Register 0.
It is also automatically reloaded on the clock cycle after it
reaches zero, the terminal count value. The value in
Data Register 2 (compare value) is continually compared
to Data Register 0 (count value) to establish the output
pulse-width (duty cycle). Reading Data Register 0 to
obtain the current value of the down counter may occur
only when the function is disabled. When read, this
transfers the value from Data Register 0 to Data Register
2 and returns a 0 on the data bus. The value transferred
to Data Register 2 can then be directly read by the CPU.
However, reading the count value in this manner will
overwrite any previously written compare value in Data
Register 2. Control Register 0 contains one bit to
enable/disable the function.
9.5.2.3
Inputs
There are two primary inputs, the Source Clock and the
Enable signal. When the Enable signal is high, the down
counter is decremented on the rising-edge of the Source
Clock. The multiplexers selecting these inputs are con-
trolled by the PSoC block Input Register (DBA00IN-
DCA07IN).
9.5.2.4
Outputs
The counter function drives its primary output signal,
Compare True, high on the falling edge of the Source
Clock when the value in Data Register 0 is less (or less
than or equal to) the value in Data Register 2. The duty
cycle of the pulse-width modulator formed in this way is
the ratio of Data Register 2 (or Data Register 2 minus
one) to Data Register 1. The choice of compare opera-
tors is determined by the MODE[1] bit. The Compare
value can be routed to additional analog or digital PSoC
blocks or via Global Output lines The auxiliary output sig-
nal is the Terminal Count signal which can be routed via
Global Output lines. The PSoC block Output Register
(DBA00OU-DCA07OU) controls output options.
9.5.2.5
Interrupts
Interrupts may be generated in either of two ways. First,
the PSoC block may optionally generate an interrupt on
the rising edge of Terminal Count or the rising edge of
the Compare signal. The selection of interrupt source is
determined by the MODE[0] bit of the PSoC block Func-
tion Register (DBA00FN-DCA07FN). The MODE[1] bit
controls whether the comparison operation is “l(fā)ess than”
or “l(fā)ess than or equal to.”
9.5.2.6
Usage Notes
1.
Enable Input
The enable input is synchronous and when low
forces the counter into a ‘hold’ state. Outputs are
unaffected by the state of the enable input. If an
external source is selected as the enable input, it is
synchronized to the 24 MHz clock.
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