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| 型號： | PSOC |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 8-Bit Programmable System-on-Chip (PSoC⑩) Microcontrollers |
| 中文描述： | 8位可編程系統(tǒng)（的PSoC⑩）微控制器片上 |
| 文件頁數(shù)： | 19/148頁 |
| 文件大?。?/td> | 1412K |
| 代理商： | PSOC |
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CPU Architecture
September 5, 2002
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
19
2.0
CPU Architecture
2.1
Introduction
This family of microcontrollers is based on a high perfor-
mance, 8-bit, Harvard architecture microprocessor. Five
registers control the primary operation of the CPU core.
These registers are affected by various instructions, but
are not directly accessible through the register space by
the user. For more details on addressing with the register
space, see section
4.0
.
The 16 bit Program Counter Register (CPU_PC) allows
for direct addressing of the full 16 Kbytes of program
memory space available in the largest members of this
family. This forms one contiguous program space, and
no paging is required.
The Accumulator Register (CPU_A) is the general-pur-
pose register that holds the results of instructions that
specify any of the source addressing modes.
The Index Register (CPU_X) holds an offset value that is
used in the indexed addressing modes. Typically, this is
used to address a block of data within the data memory
space.
The Stack Pointer Register (CPU_SP) holds the address
of the current top-of-stack in the data memory space. It is
affected by the PUSH, POP, LCALL, CALL, RETI, and
RET instructions, which manage the software stack. It
can also be affected by the SWAP and ADD instructions.
The Flag Register (CPU_F) has three status bits: Zero
Flag bit [1]; Carry Flag bit [2]; Supervisory State bit [3].
The Global Interrupt Enable bit [0] is used to globally
enable or disable interrupts. An extended I/O space
address, bit [4], is used to determine which bank of the
register space is in use. The user cannot manipulate the
Supervisory State status bit [3]. The flags are affected by
arithmetic, logic, and shift operations. The manner in
which each flag is changed is dependent upon the
instruction being executed (i.e., AND, OR, XOR... See
Table 23 on page 25
).
Table 7:
CPU Registers and Mnemonics
Register
Mnemonic
Flags
CPU_F
Program Counter
CPU_PC
Accumulator
CPU_A
Stack Pointer
CPU_SP
Index
CPU_X
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