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| 型號(hào)： | PSOC |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 8-Bit Programmable System-on-Chip (PSoC⑩) Microcontrollers |
| 中文描述： | 8位可編程系統(tǒng)（的PSoC⑩）微控制器片上 |
| 文件頁(yè)數(shù)： | 65/148頁(yè) |
| 文件大小： | 1412K |
| 代理商： | PSOC |
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Digital PSoC Blocks
September 5, 2002
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
65
9.5.4.6
Determining the Polynomial
A simple linear-feedback shift register, or LFSR, uses an
XOR gate to “add” the values of one or more bits and
feed the result back into the least-significant bit. One
possible realization of a 6-bit LFSR providing a maximal
sequence of 63 six-bit values is shown here:
The PRS function utilizes a different “modular” architec-
ture with one XOR gate between each bit of the shift reg-
ister. A maximal sequence equivalent to that produced
by the previous realization is generated by the following
modular LFSR
Denote the first implementation as a (6, 1) LFSR, where
6 gives the length of the output codes and 1 indicates the
tap which feeds the XOR gate along with the final bit.
Then the modular form just shown is denoted as a [6, 5]
LFSR. In general, the equivalent modular form of a sim-
ple N bit LFSR with M taps denoted by (N, t
1
, t
2
, …, t
M
) is
given by the notation [N, N-t
1
, N-t
2
, …, N-t
M
]. Once the
form (and thus the notation) is determined, the value of
Data Register 1 is easily determined. The bit corre-
sponding to the length and all tap bits are turned on; the
others are zero. Thus, the polynomial specification for
Data Register 1 to implement a [6, 5] LFSR is
00110000b, or 30h. A maximal sequence PRS for 8-bits
giving 255 codes is [8, 4, 3, 2] with polynomial
10001110b or 8Eh.
9.5.4.7
Usage Notes
1.
Disabled State
When the Control Register Enable bit is set to ‘0’,
the internal block clock is turned off. A write to Data
Register 2 (Seed) is loaded directly into Data Regis-
ter 0 (LFSR) to initialize or reset the seed value. All
outputs are low and the block interrupt is held low.
2.
Reading the LFSR
The current LFSR value can only be read when the
block is disabled by setting the Control Register bit 0
to low. Each byte of the current LFSR value (in the
case of a multi-byte block) must be read individually.
The Data Register 0 byte (LFSR), which returns 0,
then the Data Register 1 byte, which returns the
actual value.
9.5.5
CRC - Cyclic Redundancy Check
9.5.5.1
Summary
The CRC uses a shift register and XOR gates like the
PRS function. However, instead of an output bit stream,
the CRC function expects an input bit stream. Function-
ally the CRC block is identical to the PRS with the excep-
tion of the selected input data. Input data must be
presented synchronously to the clock. A polynomial
specification permits the length of the input sequence
over which the cyclic redundancy check computes a
result to be varied. CRC-configured PSoC blocks can be
chained to form longer results.
9.5.5.2
Registers
Data Register 0 implements a linear-feedback shift regis-
ter. Data Register 2 holds the “seed” value and when the
block is disabled, a write to Data Register 2 is loaded
Figure 13: Polynomial LFSR
1
2
3
4
5
6
+
Figure 14: Polynomial PRS
B
+
+
+
+
+
+
+
1
2
3
4
5
6
7
8
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