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| 型號： | PSOC |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 8-Bit Programmable System-on-Chip (PSoC⑩) Microcontrollers |
| 中文描述： | 8位可編程系統(tǒng)（的PSoC⑩）微控制器片上 |
| 文件頁數(shù)： | 118/148頁 |
| 文件大?。?/td> | 1412K |
| 代理商： | PSOC |
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Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet
118
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
September 5, 2002
11.7
Internal Voltage Reference
An internal bandgap voltage reference source is pro-
vided on-chip. This reference is used for the Supply Volt-
age Monitor, and can also be accessed by the user as a
reference voltage for analog operations. There is a
Bandgap Oscillator Trim Register (BDG_TR) used to cal-
ibrate this reference into specified tolerance. Factory-
programmed trim values are available for 5.0V and 3.3V
operation. The 5.0V value is loaded in the BDG_TR reg-
ister upon reset. This register must be adjusted when
operating voltage outside the range for which factory cal-
ibration was set. Changing the factory-programmed trim
value is done using the Table Read Supervisor Call rou-
tine, and is documented in
11.8
.
Bandgap Trim Register (BDG_TR, Address = Bank 1, EAh)
11.8
Supervisor ROM/System Supervisor Call Instruction
The parts in this family have a Supervisor ROM to man-
age the programming, erasure, and protection of the on-
chip Flash user program space. The Supervisor ROM
also gives the user the capability to read the internal
product ID, access factory trim values, as well as calcu-
late checksums on blocks of the Flash memory space.
The System Supervisor Call instruction (SSC, opcode/
byte 00h) provides the method for the user to access the
pre-existing routines in the Supervisor ROM to imple-
ment these functions. This instruction sets the Flags
Register (CPU_F) bit 3 to 1 and performs an interrupt to
address 0000 into the Supervisory ROM. The flag and
old PC are pushed onto the Stack. The fact that the flag
pushed has F[3] = 1 is irrelevant as the
RETI
instruction
always clears F[3]. The Supervisory code at 0000 does a
JACC
table lookup based on the Accumulator value,
which is effectively another level of instruction encoding.
This service table implements the vectors to the various
supervisory functions. The user must set several param-
eters when utilizing these functions. The parameters are
written to 5 bytes of an 8-byte block near the top of RAM
memory space.
Access to these functions must be through the Flash
APIs provided in PSoC Designer and described in Appli-
cation Note AN2015.
The following table documents each function, as well as
the required parameter values:
Table 96:
Bandgap Trim Register
Bit #
7
6
5
4
3
2
1
0
POR
FS
1
FS
1
FS
1
FS
1
FS
1
FS
1
FS
1
FS
1
Read/Write
W
W
W
W
W
W
W
W
Bit Name
FMRD
BGT[2]
BGT[1]
BGT[0]
BGO[3]
BGO[2]
BGO[1]
BGO[0]
Bit 7
:
FMRD
0 = Enable voltage divider between BG and Flash (User must not use other than this setting)
1 = Disable voltage divider between BG and Flash (Test purposes only)
Bit [6:4]
:
BGT [2:0]
Provides Temperature Curve compensation
Bit [3:0]
:
BGO [3:0]
Provides +/- 5% Offset Trim to center Vbg to 1.30V
1.
FS = Factory set trim value
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