參數(shù)資料
型號： PSOC
廠商： Cypress Semiconductor Corp.
英文描述： 8-Bit Programmable System-on-Chip (PSoC⑩) Microcontrollers
中文描述： 8位可編程系統(tǒng)（的PSoC⑩）微控制器片上
文件頁數(shù)： 113/148頁
文件大?。?/td> 1412K
代理商： PSOC
Special Features of the CPU
September 5, 2002
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
113
11.3.2
Power On Reset (POR)
Power On Reset (POR) occurs every time the power to
the device is switched on. POR is released when the
supply is typically 2.2V +/-12% for the upward supply
transition, with typically 120mV of hysterisis during the
power on transient. Bit 4 of the Status and Control Regis-
ter (CPU_SCR) is set to record this event (the register
contents are set to 00010000 by the POR). After a POR,
the microprocessor is suspended for 64 ms. This pro-
vides time for the Vcc supply to stabilize after the POR
trip, before CPU operation begins. If the Vcc voltage
drops below the POR downward supply trip point (2.1V
+/-12%, once the internal reference is established), POR
is reasserted.
Important
: The PORS status bit is set at POR and can
only be cleared by the user, and cannot be set by firm-
ware.
11.3.3
Execution Reset
The following diagram illustrates the sequence of events
(in time) for execution reset, from voltage stabilization on
through execution of user’s code. Once voltage trips
POR and after 64 ms, the CPU starts boot calibration.
Boot calibration takes 2,502 cycles, with the CPU run-
ning at 3 MHz. This results in approximately 800
μ
s for
the time between beginning boot calibration and reset
vector. At reset vector, the boot.asm must execute
before user code begins running. (boot.asm contains
device configurations from PSoC Designer. The time it
takes boot.asm to execute varies depending on device
configuration settings such as CPU speed.)
11.3.4 External Reset (X
res
)
Pulling the X
res
pin high for a minimum of 10 μS forces
the microcontroller to perform a Power On Reset (POR).
The X
res
pin does not require a pull-down resistor for
operation and can be tied directly to ground, or left open.
11.3.5 Watchdog Timer Reset (WDR)
The user has the option to enable the WDT. The WDT is
enabled by clearing the PORS bit. Once the PORS bit is
cleared, the Watchdog Timer (WDT) cannot be disabled.
The only exception to this is if a POR event takes place,
which will disable the WDT.
The sleep timer is used to generate the sleep time period
and the watchdog time period. The sleep timer divides
down the
32K
system clock, and thereby produces the
sleep time period. The user can program the sleep time
period to be one of 4 multiples of the period of the
32K
clock. When the sleep time elapses (sleep timer over-
flows), an interrupt to the Sleep Timer Interrupt Vector
will be generated.
Figure 30: Execution Reset
3.0V (Good)
V
cc
Power
3.0 - 5.5
64 ms
2502
~
Boot
Calibration
Start CPU
3 MHz
Reset
Vector
boot.asm
User Code
POR 2.2V ± 12%
T
rVdd
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