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| 型號(hào)： | PSOC |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 8-Bit Programmable System-on-Chip (PSoC⑩) Microcontrollers |
| 中文描述： | 8位可編程系統(tǒng)（的PSoC⑩）微控制器片上 |
| 文件頁(yè)數(shù)： | 63/148頁(yè) |
| 文件大?。?/td> | 1412K |
| 代理商： | PSOC |
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Digital PSoC Blocks
September 5, 2002
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
63
2.
Disabled State
When the Control Register Enable bit is set to ‘0’,
the internal block clock is turned off. A write to Data
Register 1 (Period) is loaded directly into Data Reg-
ister 0 (Counter) to initialize or reset the count. All
outputs are low and the block interrupt is held low.
Disabling a counter does not affect the current count
value and it may be read by the CPU. Two reads are
required to read each byte of a multi-byte register.
One to transfer each Data Register 0 count value to
the associated Data Register 2 capture register,
then one to read the result in Data Register 2.
3.
Reading the Count Value
A CPU read of Data Register 0 (count value) will
overwrite Data Register 2 (compare value). There-
fore, when reading the current count, a previously
written compare value will be overwritten.
4.
Extra Count
In a Counter User Module, the data input is an
enable for counting. Normally, when the enable
goes low, the counter will hold the current count.
However, if the enable happens to go low in the
same clock period as Terminal Count (count of all
0's), one additional count will occur that will reload
the counter from the Period Register. Once the
counter is reloaded from the Period Register, count-
ing will stop.
9.5.3
Deadband Generator
9.5.3.1
Summary
The Deadband function produces two output waveforms,
F0 and F1, with the same frequency as the input, but
“under-lapped” so they are never both high at the same
time. An 8-bit down counter controls the length of the
“dead time” during which both output signals are low.
When the deadband function detects a rising edge on
the input waveform, the F1 output signal goes low and
the counter decrements from its initial value to its termi-
nal count. When the down counter reaches zero, the F0
output signal goes high. The process reverses on the
falling edge of the input waveform so that after the same
dead time, F1 goes high until the input signal transitions
again. Dead-band generator PSoC blocks cannot be
chained to increase the width of the down counter
beyond 8 bits or 256 dead-time “ticks.”
9.5.3.2
Registers
Data Register 1 stores the count that controls the
elapsed dead time. Data Register 0 holds the current
state of the dead-time down counter. If the function is
disabled, writing a period into Data Register 1, will auto-
matically load Data Register 0 with the deadband period.
This period is automatically re-loaded into the counter on
each edge of the input signal. Data Register 2 is unused.
Control Register 0 contains one bit to enable/disable the
function.
9.5.3.3
Inputs
The input controls the period and duty cycle of the dead-
band generator outputs. This input is fixed to be derived
from the primary output of the previous block. If this sig-
nal is pulse-width modulated, i.e., if a PWM block is con-
figured as the previous block, the dead-band outputs will
be similarly modulated. The F0 output corresponds to
the duty cycle of the input (less the dead time) and F1 to
the duty cycle of the inverted input (again, less the dead
time). The clock input to the dead-band generator con-
trols the rate at which the down counter is decremented.
The primary data input is the “Kill” Signal. When this sig-
nal is asserted high, both F0 and F1 outputs will go low.
The multiplexers selecting these input are controlled by
the PSoC block Input Register (DBA00IN-DCA07IN).
9.5.3.4
Outputs
Both the F0 and F1 outputs can be driven onto the Glo-
bal Output bus. If the next PSoC block selects “Previous
PSoC block” for its clock input, it only “sees” the F0 out-
put of the dead-band function. The PSoC block Output
Register (DBA00OU-DCA07OU) controls output options.
9.5.3.5
Interrupts
The rising edge of the F0 signal provides the interrupt for
this block.
9.5.3.6
Usage Notes
1.
Constraints
The dead time must not exceed the minimum of the
input signal’s pulse-width high and pulse-width low
time, less two CPU clocks. Dead time equals the
period of the input clock times one plus the value
written to Data Register 1.
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