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| 型號： | PSOC |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 8-Bit Programmable System-on-Chip (PSoC⑩) Microcontrollers |
| 中文描述： | 8位可編程系統(tǒng)（的PSoC⑩）微控制器片上 |
| 文件頁數(shù)： | 36/148頁 |
| 文件大小： | 1412K |
| 代理商： | PSOC |
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Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet
36
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
September 5, 2002
Internal Low Speed Oscillator Trim Register (ILO_TR, Address = Bank 1, E9h)
7.1.3
External Crystal Oscillator
The XtalIn and XtalOut pins support connection of a
32.768 kHz watch crystal to drive the 32K clock. To con-
nect to the external crystal, the XtalIn and XtalOut pins’
drive modes must be set to High Z. To enable the exter-
nal crystal oscillator, bit 7 of the Oscillator Control 0 Reg-
ister (OSC_CR0) must be set (default is off). Note that
the Internal Low Speed Oscillator continues to run when
this external function is selected. It runs until the oscilla-
tor is automatically switched over when the sleep timer
reaches terminal count. External feedback capacitors to
V
cc
are required.
The firmware steps involved in switching between the
Internal Low Speed Oscillator and External Crystal Oscil-
lator are as follows:
1.
At reset, the chip begins operation using the Internal
Low Speed Oscillator.
2.
User immediately selects a sleep interval of 1 sec-
ond in the Oscillator Control 0 Register (OSC_CR0),
as the oscillator stabilization interval.
3.
User selects External Crystal Oscillator by setting bit
[7] in Oscillator Control 0 Register (OSC_CR0) to 1.
4.
The External Crystal Oscillator becomes the
selected 32.768 kHz source at the end of the 1-sec-
ond interval, created by the Sleep Interrupt logic.
The 1-second interval gives the oscillator time to
stabilize before it becomes the active source. The
Sleep Interrupt need not be enabled for the switch
over to occur. The user may want to reset the sleep
timer (if this does not interfere with any ongoing
real-time clock operation), to guarantee the interval
length.
5.
The user must wait the 1-second stabilization period
prior to engaging the PLL mode to lock the Internal
Main Oscillator frequency to the External Crystal
Oscillator frequency.
If the proper settings are selected in PSoC Designer, the
above steps are automatically done in
boot.asm
.
Note
: Transitions between oscillator domains may pro-
duce glitches on the 32K clock bus. Functions that
require accuracy on the 32K clock should be enabled
after the transition in oscillator domains.
The External Crystal Oscillator Trim Register (ECO_TR)
sets the adjustment for the External Crystal Oscillator.
The value placed in this register at reset is based on fac-
tory testing. This register does not adjust the frequency
of the External Crystal Oscillator. It is recommended that
the user not alter this value.
Table 36:
Internal Low Speed Oscillator Trim Register
Bit #
7
6
5
4
3
2
1
0
POR
0
0
FS
1
1.
FS = Factory set trim value
FS
1
FS
1
FS
1
FS
1
FS
1
Read/
Write
--
W
W
W
W
W
W
W
Bit Name
Reserved
Disable
ILO Trim
[5]
ILO Trim
[4]
ILO Trim
[3]
ILO Trim
[2]
ILO Trim
[1]
ILO Trim
[0]
Bit 7
:
Reserved
Bit 6
:
Disable
0 = Low Speed Oscillator is on
1 = Low Speed Oscillator is off (minimum power state)
Bit [5:0]
:
ILO Trim
[5:0]
Data value stored will alter the trimmed frequency of the Internal Low Speed Oscillator. (Not
recommended for customer alteration)
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