
CPU Architecture
September 5, 2002
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
25
2.4
Instruction Set Summary
Table 23:
Instruction Set Summary (Sorted by Mnemonic)
O
09
0A
0B
0C
0D
0E
0F 10
01
02
03
04
05
06
07 10
38
21 4
22 6
23 7
24 7
25 8
26 9
27 10
70 4
41 9
42 10
64 4
65 7
66 8
67 4
68 7
69 8
9x 11
39 5
3A 7
3B 8
3C 8
3D 9
73 4
78 4
79 4
7A 7
7B 8
30
74 4
75 4
Note
: Interrupt acknowledge to Interrupt Vector table = 13 cycles.
C
B
Instruction Format
Flags
O
76 7
77
Fx 13
Ex
Cx
8x
Dx
Bx
Ax
7C 13
7D
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F 10
60
61
62
63
3E 10
3F 10
40
29
2A
2B
2C
2D
2E
2F 10
43
44 10
71
C
B
Instruction Format
Flags
O
20
18
10
08
7E 10
7F
6A
6B
6C
28
6D
6E
6F
19
1A 6
1B 7
1C 7
1D 8
1E 9
1F
00
11
12
13
14
15
16
17
4B
4C 7
4D 7
4E 5
47
48
49
4A 10
72
31
32
33
34
35
36
37
45
46
C
B
Instruction Format
Flags
4
6
7
7
8
9
2 ADC A, expr
2 ADC A, [expr]
2 ADC A, [X+expr]
2 ADC [expr], A
2 ADC [X+expr], A
3 ADC [expr], expr
3 ADC [X+expr], expr
2 ADD A, expr
2 ADD A, [expr]
2 ADD A, [X+expr]
2 ADD [expr], A
2 ADD [X+expr], A
3 ADD [expr], expr
3 ADD [X+expr], expr
2 ADD SP, expr
2 AND A, expr
2 AND A, [expr]
2 AND A, [X+expr]
2 AND [expr], A
2 AND [X+expr], A
3 AND [expr], expr
3 AND [X+expr], expr
2 AND F, expr
3 AND reg[expr], expr
3 AND reg[X+expr], expr
1 ASL A
2 ASL [expr]
2 ASL [X+expr]
1 ASR A
2 ASR [expr]
2 ASR [X+expr]
2 CALL
2 CMP A, expr
2 CMP A, [expr]
2 CMP A, [X+expr]
3 CMP [expr], expr
3 CMP [X+expr], expr
1 CPL A
1 DEC A
1 DEC X
2 DEC [expr]
2 DEC [X+expr]
1 HALT
1 INC A
1 INC X
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
2 INC [expr]
2 INC [X+expr]
2 INDEX
2 JACC
2 JC
2 JMP
2 JNC
2 JNZ
2 JZ
3 LCALL
3 LJMP
1 MOV X, SP
2 MOV A, expr
2 MOV A, [expr]
2 MOV A, [X+expr]
2 MOV [expr], A
2 MOV [X+expr], A
3 MOV [expr], expr
3 MOV [X+expr], expr
2 MOV X, expr
2 MOV X, [expr]
2 MOV X, [X+expr]
2 MOV [expr], X
1 MOV A, X
1 MOV X, A
2 MOV A, reg[expr]
2 MOV A, reg[X+expr]
3 MOV [expr], [expr]
2 MOV reg[expr], A
2 MOV reg[X+expr], A
3 MOV reg[expr], expr
3 MOV reg[X+expr], expr
2 MVI A, [ [expr]++ ]
2 MVI [ [expr]++ ], A
1 NOP
2 OR A, expr
2 OR A, [expr]
2 OR A, [X+expr]
2 OR [expr], A
2 OR [X+expr], A
3 OR [expr], expr
3 OR [X+expr], expr
3 OR reg[expr], expr
3 OR reg[X+expr], expr
2 OR F, expr
C, Z
C, Z
Z
5
5
4
4
1 POP X
1 POP A
1 PUSH X
1 PUSH A
1 RETI
1 RET
1 RLC A
2 RLC [expr]
2 RLC [X+expr]
1 ROMX
1 RRC A
2 RRC [expr]
2 RRC [X+expr]
2 SBB A, expr
2 SBB A, [expr]
2 SBB A, [X+expr]
2 SBB [expr], A
2 SBB [X+expr], A
3 SBB [expr], expr
3 SBB [X+expr], expr
1 SSC
2 SUB A, expr
2 SUB A, [expr]
2 SUB A, [X+expr]
2 SUB [expr], A
2 SUB [X+expr], A
3 SUB [expr], expr
3 SUB [X+expr], expr
1 SWAP A, X
2 SWAP A, [expr]
2 SWAP X, [expr]
1 SWAP A, SP
3 TST [expr], expr
3 TST [X+expr], expr
3 TST reg[expr], expr
3 TST reg[X+expr], expr
2 XOR F, expr
2 XOR A, expr
2 XOR A, [expr]
2 XOR A, [X+expr]
2 XOR [expr], A
2 XOR [X+expr], A
3 XOR [expr], expr
3 XOR [X+expr], expr
3 XOR reg[expr], expr
3 XOR reg[X+expr], expr
8
Z
7
5
C, Z
5
5
5
5
8
4
7
8
11
4
7
8
4
C, Z
C, Z
C, Z
Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
4
6
7
7
8
9
7
4
4
5
6
5
6
8
9
4
6
7
5
4
4
6
7
Z
Z
Z
5
Z
Z
Z
Z
Z
Z
Z
10
15
4
6
7
7
8
9
10
5
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
Z
Z
C, Z
Z
Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
Z
Z
Z
5
6
8
9
Z
Z
Z
Z
Z
if (A=B) Z=1
if (A<B) C=1
Z
8
9
9
4
4
6
7
7
8
9
Z
Z
Z
Z
Z
Z
Z
Z
Z
C, Z
4
4
6
7
7
8
9
10
9
10
C, Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
C, Z
C, Z
C, Z
C, Z
9
9
C, Z
C, Z
4