參數(shù)資料
型號： PSOC
廠商： Cypress Semiconductor Corp.
英文描述： 8-Bit Programmable System-on-Chip (PSoC⑩) Microcontrollers
中文描述： 8位可編程系統(tǒng)（的PSoC⑩）微控制器片上
文件頁數(shù)： 121/148頁
文件大?。?/td> 1412K
代理商： PSOC
Special Features of the CPU
September 5, 2002
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
121
11.10.1 Data File Read
The user’s data file should be read into the programmer.
The checksum should be calculated by the programmer
for each record and compared to the record checksum
stored in the file for each record. If there is an error, a
message should be sent to the user explaining that the
file has a checksum error and the programming should
not be allowed to continue.
11.10.2 Programmer Flow
The following sequence (with descriptions) is the main
flow used to program the devices: (Note that failure at
any step will result in termination of the flow and an error
message to the device programmer’s operator.)
11.10.2.1
Verify Silicon ID
The silicon ID is read and verified against the expected
value. If it is not the expected value, then the device is
failed and an error message is sent to the device pro-
grammer’s operator.
This test will detect a bad connection to the programmer
or an incorrect device selection on the programmer.
The silicon ID test is required to be first in the flow and
cannot be bypassed. The sequence is as follows:
Set Vcc=0V
Set SDATA=HighZ
Set SCLK=VILP
Set Vcc=Vccp
Start the programmer’s SCLK driver
“free running”
WAIT-AND-POLL
ID-SETUP
WAIT-AND-POLL
READ-ID-WORD
Notes
: See “DC Specifications“ table in section 13 for
value of Vccp and VILP. See “AC Specifications” table in
section 13 for value of frequency for the SCLK driver
(Fsclk).
11.10.2.2
Erase
The Flash memory is erased. This is accomplished by
the following sequence:
SET-CLK-FREQ(num_MHz_times_5)
Erase All
WAIT-AND-POLL
11.10.2.3
Program
The Flash is programmed with the contents of the user’s
programming file. This is accomplished by the following
sequence:
For num_block = 0 to max_data_block
For address =0 to 63
WRITE-BYTE(address,data):
End for address loop
SET-CLK-FREQ(num_MHz_times_5)
SET-BLOCK-NUM(num_block)
PROGRAM-BLOCK
WAIT-AND-POLL
End for num_block loop
11.10.2.4
Verify (at Low Vcc and High Vcc)
The device data is read out to compare to the data in the
user’s programming file. This is accomplished by the fol-
lowing sequence:
For num_block = 0 to max_data_block
SET-BLOCK-NUM (num_block)
VERIFY-SETUP
Wait & POLL the SDATA for a high to
low transition
For address =0 to max_byte_per_block
READ-BYTE(address,data)
End for address loop
End for num_block loop
Note
: This should be done 2 times; once at Vcc=Vcclv
and once at Vcc=Vcchv.
11.10.2.5
Set Security
The security operation protects certain blocks from being
read or changed. This is done at the end of the flow so
that the security does not interfere with the verify step.
Security is set with the following sequence:
For address =0 to 63
WRITE-SECURITY-BYTE(address,data):
End for address loop
SET-CLK-FREQ(num_MHz_times_5)
SECURE
WAIT-AND-POLL
Note
: This sequence is done at Vcc=Vccp.
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