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STANDARD PRODUCT
PMC-Sierra, Inc.
PM6344 EQUAD
PMC-951013
ISSUE 5
QUADRUPLE E1 FRAMER
78
Register 009H, 089H, 109H, 189H: Receive TS0 Data Link Enables
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
R/W
SACE
0
Bit 5
R
SACI
0
Bit 4
R/W
RXSA4EN
1
Bit 3
R/W
RXSA5EN
0
Bit 2
R/W
RXSA6EN
0
Bit 1
R/W
RXSA7EN
0
Bit 0
R/W
RXSA8EN
0
SACE:
The SACE bit enables the generation of an interrupt whenever there is a
change in the National bits that are not extracted to form a data link.
Changes in the National bits are not debounced, i.e. the interrupt is generated
immediately when the current value of the National bits differs from the
previous value. The value of the National bits can be read in the FRMR
International/National Bits Register.
SACI:
The SACI bit is set to logic one whenever there is a change in the National
bits that are not extracted to form a data link. The SACI bit is cleared
following a read of this register.
RXSA4EN, RXSA5EN, RXSA6EN, RXSA7EN and RXSA8EN:
The RXSAxEN bits control the extraction of a data link from the received Time
Slot 0 National Use bits (Sa4 through Sa8).
If RXDMASIG bit is set to logic one, the data link bits are terminated by the
internal HDLC receiver. If RXDMASIG is set to logic 0, the data link is
presented on RDLSIG[x]. If the RXSA4EN is logic 1, the RDLSIG[x] value is
extracted from bit 4 of Time Slot 0 of non-frame alignment signal frames. If the
RXSA8EN is logic 1, the RDLSIG[x] value is extracted from bit 8 of Time Slot
0 of non-frame alignment signal frames. The other enable bits operate in an
analogous fashion. A clock pulse is generated on RDLCLK[x] for each enable