![](http://datasheet.mmic.net.cn/330000/PM6344-RI_datasheet_16444359/PM6344-RI_120.png)
STANDARD PRODUCT
PMC-Sierra, Inc.
PM6344 EQUAD
PMC-951013
ISSUE 5
QUADRUPLE E1 FRAMER
107
Register 020H, 0A0H, 120H, 1A0H: FRMR Frame Alignment Options
Bit
Type
Function
Default
Bit 7
R/W
CRCEN
0
Bit 6
R/W
CASDIS
0
Bit 5
R/W
AFAA
0
Bit 4
R/W
CHKSEQ
0
Bit 3
R/W
CASA
0
Bit 2
R/W
REFR
0
Bit 1
R/W
REFCRCE
0
Bit 0
R/W
REFRDIS
0
This register selects the various framing formats and framing algorithms
supported by the FRMR block.
CRCEN:
The CRCEN bit enables the FRMR to frame to the CRC multiframe. When the
CRCEN bit is logic 1, the FRMR searches for CRC multiframe alignment and
monitors for errors in the alignment. A logic 0 in the CRCEN bit position
disables searching for multiframe and suppresses the CRCE, CMFER, and
FEBE FRMR status's, forcing them to logic 0 and forcing OOCMF to a logic 1.
CASDIS:
The CASDIS bit enables the FRMR to frame to the Channel Associated
Signaling multiframe when set to a logic 0. When CAS is enabled, the FRMR
searches for signaling multiframe alignment and monitors for errors in the
alignment. A logic 1 in the CASDIS bit position disables searching for
multiframe and suppresses the OOSMF and the SMFER FRMR outputs,
forcing them to logic 0.
AFAA:
The AFAA bit enables an alternate framing algorithm. If AFAA is a logic zero,
frame alignment is declared after a correct FAS, a logic 1 in bit 2 of time slot
0 of the next frame and finally another FAS in the third frame are found. If one
of the conditions fails, the next bit position is checked for valid framing. If
AFAA is a logic one, the framing is similar to the above, but adds a "hold-off"
feature. If bit2 or the second 7-bit FAS conditions fail, the same byte location