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STANDARD PRODUCT
PMC-Sierra, Inc.
PM6344 EQUAD
PMC-951013
ISSUE 5
QUADRUPLE E1 FRAMER
98
Registers 017H, 097H, 117H and 197H: Channel Select (24 to 31)
Bit
Type
Function
Default
Bit 7
R/W
CH[31]
0
Bit 6
R/W
CH[30]
0
Bit 5
R/W
CH[29]
0
Bit 4
R/W
CH[28]
0
Bit 3
R/W
CH[27]
0
Bit 2
R/W
CH[26]
0
Bit 1
R/W
CH[25]
0
Bit 0
R/W
CH[24]
0
These registers determine which timeslots (TS) are presented on RDLSIG[x] or
inserted from TDLSIG[x] when the RFRACE1 or TFRACE1 register bit is set to
logic 1 respectively.
If the RFRACE1 register bit is a logic 1, each channel, overhead, or datalink
timeslot for which the associated CH[x] bit is set (e.g. CH[16] corresponds to
TS16) will be presented on the RDLSIG[x] output. The RDLCLK[x] output will
generate a pulse for each extracted bit.
If the TFRACE1 register bit is a logic 1, the serial stream input on TDLSIG[x] will
replace the channel timeslot from BTPCM[x] for which the associated CH[x] bit is
set. The TDLCLK[x] output will generate a pulse to clock in each defined bit.
Note that if CH[0] is set to logic 1, the TDLSIG[x] input will overwrite any framing
and overhead data that would otherwise be inserted into TS0 by the TRAN block.
If CH[16] is set to logic 1, the TDLSIG[x] input will be inserted into TS16
regardless of the settings of the SIGEN and DLEN bits of the TRAN
Configuration register.