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STANDARD PRODUCT
PMC-Sierra, Inc.
PM6344 EQUAD
PMC-951013
ISSUE 5
QUADRUPLE E1 FRAMER
25
Pin Name
Type
Pin No.
Function
CSB
Input
44
Active low chip select (CSB). This signal must be low to
enable EQUAD register accesses. This signal must be
toggled high to clear the PMCTST register bit (register
00BH or 20BH) and to ensure the EQUAD will operate
in normal mode.
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
I/O
46
47
48
49
54
55
56
57
Bi-directional data bus (D[7:0]). This bus is used during
EQUAD read and write accesses.
RDB
Input
43
Active low read enable (RDB). This signal is pulsed low
to enable a EQUAD register read access. The EQUAD
drives the D[7:0] bus with the contents of the addressed
register while RDB and CSB are both low.
WRB
Input
42
Active low write strobe (WRB). This signal is pulsed low
to enable a EQUAD register write access. The D[7:0]
bus contents are clocked into the addressed normal
mode register on the rising edge of WRB while CSB is
low.
ALE
Input
41
Address latch enable (ALE). This signal latches the
address bus contents, A[9:0], when low, allowing the
EQUAD to be interfaced to a multiplexed address/data
bus. When ALE is high, the address latches are
transparent. ALE has an integral pull-up.
RSTB
Input
40
Active low reset (RSTB). This signal is set low to
asynchronously reset the EQUAD. RSTB is a Schmitt-
trigger input with integral pull-up.
A[0]
A[1]
A[2]
A[3]
A[4]
A[5]
A[6]
A[7]
A[8]
A[9]
Input
30
31
32
33
34
35
36
37
38
39
Address bus (A[9:0]). This bus selects specific registers
during EQUAD register accesses.