![](http://datasheet.mmic.net.cn/330000/PM6344-RI_datasheet_16444359/PM6344-RI_251.png)
STANDARD PRODUCT
PMC-Sierra, Inc.
PM6344 EQUAD
PMC-951013
ISSUE 5
QUADRUPLE E1 FRAMER
238
2. Guaranteed by design for nominal XCLK input frequencies (49.152 MHz ± 50
ppm or 16.384 MHz ± 50 ppm).
3. MTCLK can be a jittered clock signal subject to the minimum and maximum
instantaneous frequencies and duty cycles shown. These specifications
correspond to nominal XCLK input frequencies.
4. High pulse width is measured from the 1.4 Volt points of the rise and fall
ramps. Low pulse width is measured from the 1.4 Volt points of the fall and
rise ramps.
5. XCLK accuracy is ± 50 ppm.
6. TCLKI[x] can be a jittered clock signal subject to the minimum high and low
durations tHTCLKI, tLTCLKI. These durations correspond to nominal XCLK
input frequencies.
7. When a set-up time is specified between an input and a clock, the set-up time
is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt
point of the clock.
8. When a hold time is specified between an input and a clock, the hold time is
the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt
point of the input.
Notes on Output Timing:
9. Output propagation delay time is the time in nanoseconds from the 1.4 Volt
point of the reference signal to the 1.4 Volt point of the output.
10. Output propagation delays are specified with a 50 pF load.