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STANDARD PRODUCT
PMC-Sierra, Inc.
PM6344 EQUAD
PMC-951013
ISSUE 5
QUADRUPLE E1 FRAMER
200
Figure 26
- XFDL Normal Data Sequence
Flag
D1
D2
Dn
CRC1 CRC2
Flag
D1
D1 D2
D3
D4
D2
D3
TDLINT[x]
D[7:0]
INTE
EOM
INTE
D1
INTE
Serial Data
inserted into
ESF FDL
This diagram shows the relationship between XFDL inputs and outputs for the
case where interrupts and CRC are enabled for regular data transmission. The
process is started by setting the INTE bit in the XFDL Configuration Register to
logic 1, thus enabling the TDLINT[x] signal. When TDLINT[x] goes high, the
interrupt service routine is started, which writes the first byte (D1) of the data
frame to the XFDL Transmit Data Register. When this byte begins to be shifted
out on the data link, TDLINT[x] goes high. This restarts the interrupt service
routine, and the next data byte (D2) is written to the XFDL Transmit Data
Register. When D2 begins to be shifted out on the data link, TDLINT[x] goes
high again. This cycle continues until the last data byte (Dn) of the frame is
written to the XFDL Transmit Data Register. When Dn begins to be shifted out on
the data link, TDLINT[x] again goes high. Since all the data has been sent, the
interrupt service routine sets the EOM bit in the XFDL Configuration Register to
logic 1. The TDLINT[x] interrupt should also be disabled at this time by setting
the INTE bit in the XFDL Configuration Register to logic 0. The XFDL will then
shift out the two-byte CRC word and closing flag, which ends the frame.
Whenever new data is ready, the TDLINT[x] signal can be re-enabled by setting
the INTE bit in the XFDL Configuration Register to logic 1, and the cycle starts
again.