![](http://datasheet.mmic.net.cn/330000/PM6344-RI_datasheet_16444359/PM6344-RI_39.png)
STANDARD PRODUCT
PMC-Sierra, Inc.
PM6344 EQUAD
PMC-951013
ISSUE 5
QUADRUPLE E1 FRAMER
26
Pin Name
Type
Pin No.
Function
PHA[0]
PHA[1]
PHA[2]
PHA[3]
PHA[4]
Power
18
52
89
105
121
AC power pins (PHA[4:0]). These pins must be
connected to a common, well decoupled +5V DC supply
together with the DC power pins PHD[3:0] .
PHD[0]
PHD[1]
PHD[2]
PHD[3]
Power
20
50
85
115
DC power pins (PHD[3:0]). These pins must be
connected to a common, well decoupled +5V DC supply
together with the AC power pins PHA[4:0].
PLA[0]
PLA[1]
PLA[2]
PLA[3]
PLA[4]
PLA[5]
Ground
19
53
90
106
122
1
AC ground pins (PLA[5:0]). These pins must be
connected to a common ground together with the DC
ground pins PLD[3:0].
PLD[0]
PLD[1]
PLD[2]
PLD[3]
Ground
21
51
86
116
DC ground pins (PLD[3:0]). These pins must be
connected to a common ground together with the AC
ground pins PLA[5:0].
Notes on Pin Description:
1. The PLA[5:0] and PLD[3:0] ground pins are not internally connected together.
Failure to connect these pins externally may cause malfunction or damage
the device. The PHA[4:0] and PHD[3:0] power pins are not internally
connected together. Failure to connect these pins externally may cause
malfunction or damage the device. These power supply connections must
all be utilized and must all connect to a common +5 V or ground rail, as
appropriate.
2. Inputs MENB, RSTB and ALE have integral pull-up resistors.
3. All outputs have 2 mA drive capability except for MRD and the D[7:0]
bidirectionals which have 4 mA drive capability.
4. All inputs and bidirectionals present minimum capacitive loading and operate
at TTL logic levels.
5. The TDLSIG/TDLINT[4:1] pins have integral pull-up resistors and default to
being inputs after a reset.