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STANDARD PRODUCT
PMC-Sierra, Inc.
PM6344 EQUAD
PMC-951013
ISSUE 5
QUADRUPLE E1 FRAMER
72
Register 007H, 087H, 107H, 187H: Transmit Timing Options
Bit
Type
Function
Default
Bit 7
R/W
HSBPSEL
0
Bit 6
R/W
XCLKSEL
0
Bit 5
R/W
OCLKSEL1
0
Bit 4
R/W
OCLKSEL0
0
Bit 3
R/W
PLLREF1
0
Bit 2
R/W
PLLREF0
0
Bit 1
R/W
TCLKISEL
0
Bit 0
R/W
SMCLKO
0
This register allows software to configure the options of the transmit timing
section.
HSBPSEL:
The HSBPSEL bit selects the source of the high-speed clock used in the
ELST, SIGX and TPSC blocks. This allows the EQUAD to interface to higher
rate backplanes (>2.048MHz) that are externally gapped; however, the
instantaneous backplane clock frequency must not exceed 3.0MHz. When
HSBPSEL is set to logic 1, the XCLK input signal is divided by 2 and used as
the high-speed clock to these blocks. XCLK must be driven with 49.152MHz.
When HSBPSEL is set to logic 0, the block high-speed clock is driven with
the internal 16.384MHz clock source selected by the XCLKSEL bit.
XCLKSEL:
The XCLKSEL bit selects the source of the high-speed clock used in the
CDRC, FRMR, and PMON blocks. When XCLKSEL is set to logic 1, the
XCLK input signal is used as the high-speed clock to these blocks. XCLK
must be driven with 16.384MHz. When XCLKSEL is set to logic 0, the block
high-speed clock is driven with XCLK divided by 3. XCLK must be driven with
49.152MHz.
OCLKSEL1, OCLKSEL0:
The OCLKSEL[1:0] bits select the source of the Digital Jitter Attenuator FIFO
output clock signal. When OCLKSEL1 is set to logic 1, the DJAT FIFO output
clock is driven with the input data clock driving the DJAT ICLK input. In this