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STANDARD PRODUCT
PMC-Sierra, Inc.
PM6344 EQUAD
PMC-951013
ISSUE 5
QUADRUPLE E1 FRAMER
92
Register 012H, 092H, 112H, 192H: CDRC Interrupt Status
Bit
Type
Function
Default
Bit 7
R
LCVI
X
Bit 6
R
LOSI
X
Bit 5
R
HDB3I
X
Bit 4
R
Z4DI
X
Bit 3
Unused
X
Bit 2
Unused
X
Bit 1
Unused
X
Bit 0
R
LOS
X
The LCVI, LOSI, HDB3I and Z4DI bits indicate which of the status events have
occurred since the last read of this register. A logic 1 indicates the
corresponding event was detected. These bits are cleared when the CDRC
Interrupt Status register is read.
LCVI:
The LCVI bit is asserted if a line code violation is detected. If the AMI bit of
the CDRC Configuration Register is a logic 1, LCVI becomes a logic 1 if two
consecutive marks are of the same polarity (i.e. on the same pin, RDP or
RDN). If the AMI and O162 bits of the CDRC Configuration Register are both
logic 0, LCVI becomes a logic 1 if a bipolar violation (BPV) is of the same
polarity as the previous BPV or if the BPV is not preceded by two spaces. If
the AMI bit is a logic 0 and the O162 bit is a logic 1, LCVI becomes a logic 1
if two consecutive bipolar violations are of the same polarity.
LOSI:
The LOSI bit is set high when the LOS status bit changes state.
HDB3I:
The HDB3I bit is set high if an HDB3 signature, which is a bipolar violation of
the opposite polarity of the previous bipolar violation following two spaces, is
detected in the received data stream.
Z4DI:
The Z4DI bit is set high if four consecutive spaces occur.