參數(shù)資料
型號(hào)： NS32FX164V-25
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： Advanced Imaging/Communication Signal Processors
中文描述： 16-BIT, 50 MHz, MIXED DSP, PQCC68
封裝： PLASTIC, LCC-68
文件頁(yè)數(shù)： 92/102頁(yè)
文件大?。?/td> 1053K
代理商： NS32FX164V-25
Appendix B: Instruction Execution Times
This section provides the necessary information to calculate
the instruction execution times for the NS32FX164.
The following assumptions are made:
Y
The entire instruction, with all displacements and imme-
diate operands, is assumed to be present in the instruc-
tion queue when needed.
Y
Interference from instruction prefetches, which is very
dependent upon the preceding instruction(s), is ignored.
This assumption will tend to affect the timing estimate
in an optimistic direction.
Y
It is assumed that all memory operand transfers are
completed before the next instruction begins execution.
In the case of an operand of access class rmw in
memory, this is pessimistic, as the Write transfer occurs
in parallel with the execution of the next instruction.
Y
It is assumed that there is no overlap between the
fetch of an operand and the following sequences of mi-
crocode. This is pessimistic, as the fetch of Operand 1
will generally occur in parallel with the effective address
calculation of Operand 2, and the fetch of Operand 2
will occur in parallel with the execution phase of the in-
struction.
Y
Where possible, the values of operands are taken into
consideration when they affect instruction timing, and a
range of times is given. Where this is not done, the
worst case is assumed.
B.1 BASIC AND FLOATING-POINT INSTRUCTIONS
Execution times for basic and floating-point instructions are
given in Tables B-1 and B-2. The parameters needed for the
various calculations are defined below.
TEAD The time required to calculate an operand’s Effec-
tive Address. For a Register or Immediate oper-
and, this includes the fetch of that operand.
TEA1D TEA value for the GEN or GEN1 operand.
TEA2D TEA value for the GEN2 operand.
TOPBD The time needed to read or write a memory byte.
TOPWD The time needed to read or write a memory word.
TOPDD The time needed to read or write a memory dou-
ble-word.
TOPiD The time needed to read or write a memory oper-
and, where the operand size is given by the opera-
tion length of the instruction. It is always equiva-
lent to either TOPB, TOPW or TOPD.
TCYD Internal processing overhead, in clock cycles.
LD Internal processing whose duration depends on
the operation length. The number of clock cycles
is derived by multiplying this value by the number
of bytes in the operation length.
NCYCD Number of bus cycles performed by the CPU to
fetch or store an operand. NCYC depends on the
operand size and alignment.
TPRD CPU processing (in clock cycles) performed in par-
allel with the FPU.
TFPUD Processing time required by the FPU to execute
the instruction. This is the time from the last data
sent to the FPU, until done is issued. TFPU can be
found in the FPU data sheets.
fD This parameter is related to the floating-point op-
erand size.
TfD The time required to transfer 32 bits of floating
point value to or from the FPU.
TiD The time required to transfer an integer value to or
from the FPU.
B.1.1 Equations
The following equations assume that:
#
Memory accesses occur at full speed.
#
Any wait states should be reflected in the calculations of
TOPB, TOPW and TOPD.
Note:
When multiple writes are performed during the execution of an in-
struction, wait states occurring during intermediate write transactions
may be partially hidden by the internal execution. Therefore, a certain
number of wait states can be inserted with no effect on the execution
time. For example, in the case of the MOVSi instructions each wait
state on write operations subtracts 1 clock cycle per write bus access,
from the TCY of the instruction, since updating the pointers occurs in
parallel with the write operation. This means that wait states can be
added to write cycles without changing the execution time of the in-
struction, up to a maximum of 13 wait states on writes for MOVSB and
MOVSW, and 4 wait states on writes for MOVSD.
TEAD TEA values for the various addressing modes are
provided in the following table.
TEA TABLE
Addressing
TEA
Notes
Mode
Value
IMMEDIATE,
ABSOLUTE
4
EXTERNAL
11
a
2
*
TOPD
MEMORY RELATIVE
7
a
TOPD
REGISTER
2
REGISTER RELATIVE,
MEMORY SPACE
5
TOP OF STACK
4
2
3
Access Class Write
Access Class Read
Access Class RMW
SCALED INDEXED
TI1
a
TI2
TI1
e
TEA of the basemode except:
if basemode is REGISTER then TI1
e
5
if basemode is TOP OF STACK then TI1
e
4
TI2 depends on the scale factor:
if byte indexing TI1
e
5
if word indexing TI2
e
7
if double-word indexing TI2
e
8
if quad-word indexing TI2
e
10
TOPBD If operand is in a register or is immediate then
TOPB
e
0
else TOPB
e
3
TOPWD If operand is in a register or is immediate then
TOPW
e
0
else TOPW
e
4
#
NCYC
b
1
TOPDD If operand is in a register or is immediate then
TOPD
e
0
else TOPD
e
4
#
NCYC
b
1
92
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