參數(shù)資料
型號: NS32FX164V-25
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 數(shù)字信號處理
英文描述: Advanced Imaging/Communication Signal Processors
中文描述: 16-BIT, 50 MHz, MIXED DSP, PQCC68
封裝: PLASTIC, LCC-68
文件頁數(shù): 46/102頁
文件大小: 1053K
代理商: NS32FX164V-25
3.0 Functional Description
(Continued)
SXHDStore X Vector Pointer Higher Half
The SXH instruction stores the contents of the higher-half of
the X register into the word at mem
[
addr
]
.
Syntax:
SXH addr
15
11 10
0
11101
addr
Operation:
à
mem
[
aligned addr
] 4
X.high;
ó
Note:
Accumulator is not affected.
SYDStore Y Vector Pointer
The SY instruction stores the contents of the Y register into
the double-word at alignedDaddr.
Syntax:
SY alignedDaddr
15
11 10
0
01011
alignedDaddr
Operation:
à
(vector ptr) mem
[
aligned addr
] 4
Y;
ó
Note:
Accumulator is not affected.
SZDStore Z Vector Pointer
The SZ instruction stores the contents of the Z register into
the double-word at alignedDaddr.
Syntax:
SZ alignedDaddr
15
11 10
0
01100
alignedDaddr
Operation:
à
(vector pointer mem
[
aligned addr
] 4
Z;
ó
Note:
Accumulator is not affected.
SADStore Accumulator
The SA instruction stores the contents of the A accumulator
as a complex value into mem
[
alignedDaddr
]
.
Syntax:
SA alignedDaddr
15
11 10
0
01101
alignedDaddr
Operation:
à
(complex mem
[
aligned addr
] 4
(complex) A;
ó
Notes:
Bits 15 through 30 of the real and imaginary parts of the accumulator
are placed in the real and imaginary parts of the complex value at
mem
[
alignedDaddr
]
.
Accumulator is not affected.
SEADStore Extended Accumulator
The SEA stores the contents of bits 0–30 of the imaginary
accumulator as an extended value into a DSPM memory
location specified by Z
[
0
]
.
Bit 0 of this memory location is loaded with ‘‘0’’.
Syntax:
EXEC SEA
15
11 10
0
10000
101 0011 0110
Operation:
à
extended Z;
Z
[
0
] 4
(extended) A;
ó
Note:
Accumulator is not affected.
SREPEATDStore Repeat Register
The SREPEAT instruction stores the contents of the
REPEAT register in the double-word at mem
[
alignedD
addr
]
.
Syntax:
SREPEAT alignedDaddr
15
11 10
0
01110
alignedDaddr
Operation:
à
(repeat reg) mem
[
aligned addr
] 4
REPEAT;
ó
Note:
Accumulator is not affected.
SOVFDStore and Clear OVF Register
The SOVF instruction stores the contents of the OVF regis-
ter in the word at mem
[
addr
]
. The OVF register is then
cleared to ‘‘0’’.
Syntax:
SOVF addr
15
11 10
0
01001
addr
Operation:
à
(ovf reg) mem
[
aligned addr
] 4
OVF;
ó
Note:
Accumulator is not affected.
3.4.5.6 Adjust Register Instructions
INCXDIncrement X Vector Pointer
The INCX instruction increments the X vector pointer by one
element, according to the increment and the wrap.
Syntax:
EXEC INCX
15
11 10
0
10000
100 0101 1001
46
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