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| 型號： | NS32FX164V-25 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Advanced Imaging/Communication Signal Processors |
| 中文描述： | 16-BIT, 50 MHz, MIXED DSP, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 44/102頁 |
| 文件大小： | 1053K |
| 代理商： | NS32FX164V-25 |
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3.0 Functional Description
(Continued)
alignedDreal
An aligned real value, as described in Sec-
tion 3.4.2.4.
extended
An extended-precision real value, as de-
scribed in Section 3.4.2.5.
complex
A complex value, as described in Section
3.4.2.6.
vectorDptr
repeatDreg
paramDreg
eabrDreg
realDacc
A valid value for X, Y, and Z registers.
A valid value for REPEAT register.
A valid value for PARAM register.
A valid value for EABR register.
A 34-bit value inside either the real part or
the imaginary part of the accumulator.
complexDacc A 68-bit value inside the complex accumu-
lator.
3.4.5.3 General Notes
The values of the EABR, PARAM, X, Y, and Z registers are
not changed by the execution of the command list.
Some instructions use the accumulator as a temporary reg-
ister and therefore destroy its contents. In general, the user
should assume that the contents of the accumulator are
unpredictable after an instruction terminates, unless stated
otherwise in the notes section following that instruction’s
formal specification.
Non-complex instructions that use the accumulator, can use
either the real or the imaginary parts, or both. In general,
when an integer or real data type is to be read, it is taken
from the real part. An extended-precision real data type is
taken from the imaginary part. When a non-complex data
type is loaded into the accumulator (by the LEA instruction
or within other instructions prior to saving it into memory), it
is written to both real and imaginary parts.
Rounding is implemented by copying PARAM.RND into bit
position 14 of both the real and the imaginary part of the
accumulator, performing the requested operation, and trun-
cating the contents of the accumulator upon storing results
to memory. In Multiply-and-Add instructions and some of the
special instructions, this is done transparently on each vec-
tor element iteration. In Multiply-and-Accumulate instruc-
tions, when PARAM.CLR is ‘‘0’’, the previous content of the
accumulator is used, so that rounding control is actually per-
formed when the accumulator is first loaded and not when
the multiply operations is executed. On the other hand, if
PARAM.CLR is ‘‘1’’, the PARAM.RND value is copied into
bit 14 of the cleared accumulator, so that rounding control is
done at the same time that the multiply operation is execut-
ed.
Rounding is performed only for real, aligned-real and com-
plex data types. In operations on complex operands, the
order of accumulation is as follows: the result of the multipli-
cation with the real part of the X operand is added first to
the accumulator, and only then the result of the multiplica-
tion with the imaginary part of the X operand is added.
In general, the X, Y, and Z vectors can overlap. However,
because of the pipelined structure of the DSPM datapath,
the user must verify that a value written into the DSPM inter-
nal memory will not be used in the same vector instruction
as a source operand for the next 8 iterations, in all instruc-
tions except VCPOLY. In VCPOLY, Y
[
0
]
cannot be over-rid-
den at all.
The description below specifies the encoding of each DSPM
instruction. All other values are reserved for future use. Any
attempt to execute any reserved instructions will terminate
execution of the command list, issue an NMI request, and
set NMISTAT.UND to ‘‘1’’. In this case the contents of the
EXT and DSPMASK remain unchanged, but the contents of
the Accumulator and OVF may change.
3.4.5.4 Load Register Instructions
LXDLoad X Vector Pointer
The LX instruction loads the double-word at alignedDaddr
into the X register.
Syntax:
LX alignedDaddr
15
11 10
0
00010
alignedDaddr
Operation:
à
X
4
(vector ptr) mem
[
aligned addr
]
;
ó
Notes:
The value at mem
[
alignedDaddr
]
should conform to vector pointer
specification format.
Accumulator is not affected.
LYDLoad Y Vector Pointer
The LY instruction loads the double-word at alignedDaddr
into the Y register.
Syntax:
LY alignedDaddr
15
11 10
0
00011
alignedDaddr
Operation:
à
Y
4
(vector ptr) mem
[
aligned addr
]
;
ó
Notes:
The value at mem
[
alignedDaddr
]
should conform to vector pointer
specification format.
Accumulator is not affected.
LZDLoad Z Vector Pointer
The LZ instruction loads the double-word at alignedDaddr
into the Z register.
Syntax:
LZ alignedDaddr
15
11 10
0
00100
alignedDaddr
Operation:
à
Z
4
(vector ptr) mem
[
aligned addr
]
;
ó
Notes:
The value at mem
[
alignedDaddr
]
should conform to vector pointer
specification format.
Accumulator is not affected.
44
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