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參數(shù)資料
| 型號： | NS32FX164V-25 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Advanced Imaging/Communication Signal Processors |
| 中文描述： | 16-BIT, 50 MHz, MIXED DSP, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 67/102頁 |
| 文件大?。?/td> | 1053K |
| 代理商： | NS32FX164V-25 |
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3.0 Functional Description
(Continued)
TL/EE/11267–38
*
Note:
Slave Processor samples Data Bus here.
FIGURE 3-26. Slave Processor Write Cycle
3.5.5.8 Data Access Sequences
The 24-bit address provided by the NS32FX164 is a byte
address; that is, it uniquely identifies one of up to
16,777,216 8-bit memory locations. An important feature of
the NS32FX164 is that the presence of a 16-bit data bus
imposes no restrictions on data alignment; any data item,
regardless of size, may be placed starting at any memory
address. The NS32FX164 provides a special control signal,
High Byte Enable (HBE), which facilitates individual byte ad-
dressing on a 16-bit bus.
Memory is organized as two 8-bit banks, each bank receiv-
ing the word address (A1–A23) in parallel. One bank, con-
nected to Data Bus pins AD0–AD7, is enabled to respond
to even byte addresses; i.e., when the least significant ad-
dress bit (A0) is low. The other bank, connected to Data Bus
pins AD8–AD15, is enabled when HBE is low. See Figure
3-28.
Any bus cycle falls into one of three categories: Even Byte
Access, Odd Byte Access, and Even Word Access. All ac-
cesses to any data type are made up of sequences of these
cycles. Table 3-5 gives the state of A0 and HBE for each
category.
TL/EE/11267–39
FIGURE 3-27. NS32FX164 and FPU Interconnections
TL/EE/11267–40
FIGURE 3-28. Memory Interface
TABLE 3-5. Bus Cycle Categories
Category
HBE
A0
Even Byte
Odd Byte
Even Word
1
0
0
0
1
0
Accesses of operands requiring more than one bus cycle
are performed sequentially, with no idle T-states separating
them. The number of bus cycles required to transfer an op-
erand depends on its size and its alignment (i.e., whether it
starts on an even byte address or an odd byte address).
Table 3-6 lists the bus cycles performed for each situation.
For the timing of A0 and HBE, see Section 3.5.5.2.
67
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