參數(shù)資料
型號(hào)： NS32FX164V-25
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 數(shù)字信號(hào)處理
英文描述： Advanced Imaging/Communication Signal Processors
中文描述： 16-BIT, 50 MHz, MIXED DSP, PQCC68
封裝： PLASTIC, LCC-68
文件頁(yè)數(shù)： 40/102頁(yè)
文件大?。?/td> 1053K
代理商： NS32FX164V-25
3.0 Functional Description
(Continued)
TABLE 3-2. Summary of Exception Processing
Exception
Instruction
Ending
Cleared before
Saving PSR
Cleared after
Saving PSR
Interrupt
Before Instruction
None /P
*
TUSPI
UND
SLAVE, SVC, DVZ, FLG, BPT, ILL
TRC
Suspended
Suspended
Before Instruction
P
TUS
TUSP
TUS
None
P
3.3 DEBUGGING SUPPORT
The NS32FX164 provides features to assist in program de-
bugging.
Besides the Breakpoint (BPT) instruction that can be used
to generate soft breaks, the CPU also provides the instruc-
tion tracing capability.
3.3.1 Instruction Tracing
Instruction tracing is a very useful feature that can be used
during debugging to single-step through selected portions of
a program. Tracing is enabled by setting the T-bit in the PSR
Register. When enabled, the CPU generates a Trace Trap
(TRC) after the execution of each instruction.
At the beginning of each instruction, the T-bit is copied into
the PSR P (Trace ‘‘Pending’’) bit. If the P-bit is set at the end
of an instruction, then the Trace Trap is activated. If any
other trap or interrupt request is made during a traced in-
struction, its entire service procedure is allowed to complete
before the Trace Trap occurs. Each interrupt and trap se-
quence handles the P-bit for proper tracing, guaranteeing
only one Trace Trap per instruction, and guaranteeing that
the Return Address pushed during a Trace Trap is always
the address of the next instruction to be traced.
The beginning of the execution of a TRAP(UND) is not con-
sidered to be a beginning of an instruction, and hence the
T-bit is not copied into the P-bit.
Due to the fact that some instructions can clear the T- and
P-bits in the PSR, in some cases a Trace Trap may not
occur at the end of the instruction. This happens when one
of the privileged instructions BICPSRW or LPRW PSR is
executed.
In other cases, it is still possible to guarantee that a Trace
Trap occurs at the end of the instruction, provided that spe-
cial care is taken before returning from the Trace Trap Serv-
ice Procedure. In case a BICPSRB instruction has been ex-
ecuted, the service procedure should make sure that the
T-bit in the PSR copy saved on the Interrupt Stack is set
before executing the RETT instruction to return to the pro-
gram being traced. If the RETT or RETI instructions have to
be traced, the Trace Trap Service Procedure should set the
P- and T-bits in the PSR copy on the Interrupt Stack that is
going to be restored in the execution of such instructions.
While debugging the NS32FX164 instructions which have
interior loops (BBOR, BBXOR, BBAND, BBFOR, EXTBLT,
MOVMP, SBITPS, TBITS), special care must be taken with
the single-step trap. If an interrupt occurs during a single-
step of one of the graphics instructions, the interrupt will be
serviced. Upon return from the interrupt service routine, the
new NS32FX164 instruction will not be re-entered, due to a
single-step trap. Both the NMI and INT interrupts will cause
this behavior. Another single-step operation (S command in
DBG16/MONCG) will resume from where the instruction
was interrupted. There are no side effects from this early
termination, and the instruction will complete normally.
For all other Series 32000 instructions, a single-step opera-
tion will complete the entire instruction before traping back
to the debugger. On the instructions mentioned above, serv-
eral single-step commands may be required to complete the
instruction, ONLY when interrupts are occurring.
There are some methods to give the appearance of single-
stepping for these NS32FX164 instructions.
1. MON16/MONCG monitors the return from single-step
trap vector, PC value. If the PC has not changed since
the last single-step command was issued, the single-step
operation is repeated. It is also advisable to ensure that
one of the NS32FX164 instructions is being single-
stepped, by inspecting the first byte of the address point-
ed to by the PC register. If it is 0x0E, then the instruction
is an NS32FX164-specific instruction.
2. A breakpoint following the instruction would also trap af-
ter the instruction had completed.
Note:
If instruction tracing is enabled while the WAIT instructioin is execut-
ed, the Trap (TRC) occurs after the next interrupt, when the interrupt
service procedure has returned.
3.4 DSP MODULE
The following sections give full specifications for the
32FX164 on-chip DSP Module.
3.4.1 Programming Model
The DSPM programming model consists of the following el-
ements:
#
Internal RAM
#
Dedicated registers
#
Command-list execution unit
#
Interface with CPU core
#
Vector instruction set
The Internal RAM is used by the DSPM for fetching com-
mands to be executed, and for reading or writing data that is
needed in the course of program execution. DSPM Pro-
grams are encoded as command lists and are interpreted by
the command-list execution unit.
Computations are performed by commands selected from
the set of available ones. These commands employ the
DSP-oriented datapath in a pipelined manner, thus maximiz-
ing the utilization of on-chip hardware resources. A set of
dedicated registers is used to specify operands and options
for subsequent vector commands. These dedicated regis-
ters can be loaded and stored by appropriate commands in
between initiations of vector commands. Additional com-
mands are available for controlling the flow of execution of
the command list, as needed for programming loops and
branches (see Section 3.4.5.7).
40
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