參數(shù)資料
型號(hào)： NS32FX164V-25
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 數(shù)字信號(hào)處理
英文描述： Advanced Imaging/Communication Signal Processors
中文描述： 16-BIT, 50 MHz, MIXED DSP, PQCC68
封裝： PLASTIC, LCC-68
文件頁(yè)數(shù)： 2/102頁(yè)
文件大小： 1053K
代理商： NS32FX164V-25
Table of Contents
1.0 PRODUCT INTRODUCTION àààààààààààààààààààààà6
1.1 NS32FX164 Special Featuresàààààààààààààààààààà6
2.0 ARCHITECTURAL DESCRIPTION ààààààààààààààààà7
2.1 Register Set ààààààààààààààààààààààààààààààààààà7
2.1.1 General Purpose Registers ààààààààààààààààà7
2.1.2 Address Registers ààààààààààààààààààààààààà8
2.1.3 Processor Status Register àààààààààààààààààà8
2.1.4 Configuration Register ààààààààààààààààààààà9
2.1.5 DSP Module Registers ààààààààààààààààààààà9
2.2 Memory Organization àààààààààààààààààààààààààà11
2.2.1 Address Mappingààààààààààààààààààààààààà12
2.3 Modular Software Supportàààààààààààààààààààààà12
2.4 Instruction Set àààààààààààààààààààààààààààààààà12
2.4.1 General Instruction Format àààààààààààààààà12
2.4.2 Addressing Modesàààààààààààààààààààààààà14
2.4.3 Instruction Set Summary àààààààààààààààààà16
2.5 Graphics Supportàààààààààààààààààààààààààààààà20
2.5.1 Frame Buffer Addressing àààààààààààààààààà20
2.5.2 BITBLT Fundamentals àààààààààààààààààààà20
2.5.2.1 Frame Buffer Architectureààààààààààà21
2.5.2.2 Bit Alignmentàààààààààààààààààààààà21
2.5.2.3 Block Boundaries and Destination
Masksàààààààààààààààààààààààààààà21
2.5.2.4 BITBLT Directions ààààààààààààààààà22
2.5.2.5 BITBLT Variations ààààààààààààààààà23
2.5.3 Graphics Support Instructionsàààààààààààààà23
2.5.3.1 BITBLT (BIT-aligned BLock Transfer)à23
2.5.3.2 Pattern Fill àààààààààààààààààààààààà24
2.5.3.3 Data Compression, Expansion and
Magnifyààààààààààààààààààààààààààà24
2.5.3.3.1 Magnifying Compressed
Dataààààààààààààààààààààà26
3.0 FUNCTIONAL DESCRIPTION àààààààààààààààààààà26
3.1 Instruction Execution àààààààààààààààààààààààààà26
3.1.1 Operating States ààààààààààààààààààààààààà26
3.1.2 Instruction Endings ààààààààààààààààààààààà26
3.1.2.1 Completed Instructions ààààààààààààà27
3.1.2.2 Suspended Instructionsààààààààààààà27
3.1.2.3 Terminated Instructionsààààààààààààà27
3.1.2.4 Partially Completed Instructions ààààà27
3.1.3 Slave Processor Instructionsààààààààààààààà27
3.1.3.1 Slave Processor Protocol ààààààààààà27
3.1.3.2 Floating-Point Instructions àààààààààà28
3.2 Exception Processingàààààààààààààààààààààààààà29
3.2.1 Exception Acknowledge Sequence ààààààààà29
3.2.2 Returning from an Exception Service
Procedure ààààààààààààààààààààààààààààààà30
3.2.3 Maskable Interruptsààààààààààààààààààààààà34
3.2.3.1 Non-Vectored Mode ààààààààààààààà34
3.2.3.2 Vectored Mode: Non-Cascaded
Caseààààààààààààààààààààààààààààà35
3.2.3.3 Vectored Mode: Cascaded Caseààààà35
3.2.4 Non-Maskable Interrupt ààààààààààààààààààà37
3.2.5 Traps ààààààààààààààààààààààààààààààààààà37
3.2.6 Priority among Exceptions ààààààààààààààààà37
3.2.7 Exception Acknowledge Sequences: Detailed
Flowàààààààààààààààààààààààààààààààààààà39
3.2.7.1 Maskable/Non-Maskable Interrupt
Sequence àààààààààààààààààààààààà39
3.2.7.2 SLAVE/ILL/SVC/DVZ/FLG/BPT/UND
Trap Sequenceàààààààààààààààààààà39
3.2.7.3 Trace Trap Sequence àààààààààààààà39
3.3 Debugging Support àààààààààààààààààààààààààààà40
3.3.1 Instruction Tracingàààààààààààààààààààààààà40
3.4 DSP Module àààààààààààààààààààààààààààààààààà40
3.4.1 Programming Model àààààààààààààààààààààà40
3.4.2 RAM Organization and Data Types ààààààààà41
3.4.2.1 Integer Valuesààààààààààààààààààààà41
3.4.2.2 Aligned-Integer Values ààààààààààààà41
3.4.2.3 Real Valuesààààààààààààààààààààààà41
3.4.3.4 Aligned-Real Values ààààààààààààààà41
3.4.2.5 Extended Precision Real Values ààààà41
3.4.2.6 Complex Values ààààààààààààààààààà42
3.4.3 Command List Format àààààààààààààààààààà42
3.4.4 CPU Core Interfaceààààààààààààààààààààààà42
3.4.4.1 Synchronization of Parallel Operationà42
3.4.4.2 DSPM RAM Organization ààààààààààà43
3.4.5 DSPM Instruction Set ààààààààààààààààààààà43
3.4.5.1 Conventions àààààààààààààààààààààà43
3.4.5.2 Type Castingàààààààààààààààààààààà43
3.4.5.3 General Notesààààààààààààààààààààà44
3.4.5.4 Load Register Instructions àààààààààà44
3.4.5.5 Store Register Instructionsàààààààààà45
3.4.5.6 Adjust Register Instructions ààààààààà46
3.4.5.7 Flow Control Instructions ààààààààààà47
3.4.5.8 Internal Memory Move Instructionsààà48
3.4.5.9 External Memory Move Instructions àà48
3.4.5.10 Arithmetic/Logical Instructions ààààà49
3.4.5.11 Multiply-and-Accumulate
Instructions àààààààààààààààààààààà49
3.4.5.12 Multiply-and-Add Instructionsààààààà50
3.4.5.13 Clipping and Min/Max Instructions àà52
3.4.5.14 Special Instructions ààààààààààààààà53
2
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