參數(shù)資料
型號(hào)： NS32FX164V-25
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 數(shù)字信號(hào)處理
英文描述： Advanced Imaging/Communication Signal Processors
中文描述： 16-BIT, 50 MHz, MIXED DSP, PQCC68
封裝： PLASTIC, LCC-68
文件頁(yè)數(shù)： 43/102頁(yè)
文件大小： 1053K
代理商： NS32FX164V-25
3.0 Functional Description
(Continued)
memory areas for any purpose, exactly as they would ac-
cess external off-chip memory locations. However, when
the DSPM command list execution unit is active, any at-
tempt to read or write a location within the above memory
areas, except for accessing the CLSTAT, EXT, DSPMASK,
DSPINT, NMISTAT, or ABORT control registers (see be-
low), will be treated as follows: All read data will have unpre-
dictable values, and any attempt to write data will not
change the DSPM memory and registers. Whenever such
an access occurs, NMISTAT.ERR bit is set to ‘‘1’’, an NMI
request to the core is issued, and the command list execu-
tion terminates. In this case, as the command-list execution
terminates asyncronously, the currently executed command
may be aborted. The DSPM RAM and the A, X, Y, Z, and
REPEAT registers may hold temporary values created in
this aborted instruction.
Some of the vector instructions executable by the DSPM
can access external off-chip memory to transfer data in or
out of the internal RAM, or to reference large lookup tables.
Normally, external memory references initiated by the
DSPM and CPU core are interleaved by the CPU core bus-
arbitration logic. As a result, it is the user’s responsibility, to
make sure that whenever a write operation is involved, the
DSPM and CPU core should not reference the same exter-
nal memory locations, since the order of these transactions
is unpredictable.
Each time the DSPM needs to access the external bus, it
issues an internal HOLD request to the CPU core, and waits
for an internal HOLD acknowledge. External HOLD requests
(when the HOLD signal is asserted) have higher priority than
DSPM HOLD requests.
In order to ensure fast response for time-critical interrupt
requests, the DSPM external referencing mechanism will re-
linquish the core bus for one clock cycle after each memory
transaction. This allows the core to use the bus for one
memory transaction. To further enhance the core speed on
critical interrupt routines, the EXT.HOLD control flag is pro-
vided.
Whenever the core sets EXT.HOLD to ‘‘1’’, the DSPM stops
its external memory references. When the DSPM needs to
perform an external memory reference but is disabled, it
enters a HOLD state until a value of ‘‘0’’ is written to the
EXT.HOLD control register.
3.4.4.2 DSPM RAM Organization
The mapping of these locations to CPU core address space
is shown below, wherebase corresponds to the start of the
mapped area (address
0xFFFE0000
):
15
8
7
0
base
a
1
base
a
0
(RAM Location 0)
base
a
3
base
a
2
(RAM Location 1)
. . .
. . .
base
a
2n
a
1
base
a
2n
(RAM Locationn )
. . .
. . .
The RAM array is not restricted to use by the DSPM, but can
also be used by the core as a fast, zero wait-state, on-chip
memory for instructions and data storage. The core can ac-
cess each byte, word, or double-word of the RAM, with no
restrictions on alignment.
3.4.5 DSPM Instruction Set
3.4.5.1 Conventions
The formal description below of DSPM command-list in-
structions is based on the ‘‘C’’ programming language, us-
ing the following conventions:
low
Bits 0 through 15 of a 32 bits entity.
high
Bits 16 through 31 of a 32 bits entity.
LENG
Value of PARAM.LENGTH.
A
alignedDaddr An even number in the range
[
0, 2
16
]
, used
for specifying a double word-aligned address
in internal memory.
mem
[
k
]
A value in internal memory whose first word
address is k, where 0
s
k
k
2
16
.
extDmem
[
k
]
A value in external memory whose first byte
address is k, where 0
s
k
k
2
32
.
Accumulator.
X
Vector in internal memory whose first ad-
dress is pointed to by X.ADDR.
Y
Vector in internal memory whose first ad-
dress is pointed to by Y.ADDR.
Z
Vector in internal memory whose first ad-
dress is pointed to by Z.ADDR.
X
[
n
]
A value in internal memory whose address is
formed by adding an offset to a cyclic buffer
base address. The base address is formed
by clearing the (X.WRAP
b
1) less-signifi-
cant bits of X.ADDR. The offset within the
buffer
is
calculated
n
c
2
X.INCR
) modulo 2
X.WRAP
.
A value in internal memory whose address is
formed by adding an offset to a cyclic buffer
base address. The base address is formed
by clearing the (Y.WRAP
b
1) less-signifi-
cant bits of Y.ADDR. The offset within the
buffer
is
calculated
n
c
2
Y.INCR
) modulo 2
Y.WRAP
.
A value in internal memory whose address is
formed by adding an offset to a cyclic buffer
base address. The base address is formed
by clearing the (Z.WRAP
b
1) less-signifi-
cant bits of Z.ADDR. The offset within the
buffer
is
calculated
n
c
2
Z.INCR
) modulo 2
Z.WRAP
.
The word address of X
[
n
]
.
The word address of Y
[
n
]
.
The word address of Z
[
n
]
.
by:
(X.ADDR
a
Y
[
n
]
by:
(Y.ADDR
a
Z
[
n
]
by:
(Z.ADDR
a
&X
[
n
]
&Y
[
n
]
&Z
[
n
]
3.4.5.2 Type Casting
The following data type definitions are used in DSPM in-
struction description:
integer
An integer value, as described in Section
3.4.2.1.
alignedDinteger An aligned integer value, as described in
Section 3.4.2.2.
real
A real value, as described in Section
3.4.2.3.
43
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