參數(shù)資料
型號(hào)： NS32FX164V-25
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： Advanced Imaging/Communication Signal Processors
中文描述： 16-BIT, 50 MHz, MIXED DSP, PQCC68
封裝： PLASTIC, LCC-68
文件頁(yè)數(shù)： 45/102頁(yè)
文件大?。?/td> 1053K
代理商： NS32FX164V-25
3.0 Functional Description
(Continued)
LADLoad Accumulator
The LA instruction loads the complex value at alignedD
addr into the A accumulator as a complex value.
Syntax:
LA alignedDaddr
15
11 10
0
00101
alignedDaddr
Operation:
à
(complex) A
4
(complex) mem
[
aligned addr
]
;
ó
Notes:
The real and imaginary parts are placed in bits 15 through 30 of the
real and imaginary parts of the accumulator.
When PARAM.RND is set to ‘‘1’’, bit 14 of the real and imaginary
parts is set to ‘‘1’’, in order to implement rounding upon subsequent
additions into the accumulator. Otherwise, it is cleared to ‘‘0’’.
LEADLoad Extended Accumulator
The LEA instruction loads the accumulator with the extend-
ed value specified by X
[
0
]
.
Both the real and the imaginary parts of the accumulator are
loaded.
Syntax:
EXEC LEA
15
11 10
0
10000
101 0011 0011
Operation:
à
extended X;
A
4
(extended) X
[
0
]
;
ó
Note:
Bits 1 through 31 of the memory location are read into bit positions 0
through 30 of the accumulator.
LPARAMDLoad Parameters Register
The
alignedDaddr into the PARAM register.
Syntax:
LPARAM
instruction
loads
the
double-word
at
LPARAM alignedDaddr
15
11 10
0
00000
alignedDaddr
Operation:
à
PARAM
4
(param reg) mem
[
aligned addr
]
;
ó
Notes:
The value at mem
[
alignedDaddr
]
should conform to this register
format. The value written into PARAM.LENGTH must be greater
then 0.
Accumulator is not affected.
LREPEATDLoad Repeat Register
The
alignedDaddr into the REPEAT register.
Syntax:
LREPEAT
instruction
loads
the
double-word
at
LREPEAT alignedDaddr
15
11 10
0
00110
alignedDaddr
Operation:
à
REPEAT
4
(repeat reg) mem
[
aligned addr
]
;
ó
Notes:
The value at mem
[
alignedDaddr
]
should conform to the REPEAT
register format.
Accumulator is not affected.
LEABRDLoad External Address Base Register
The
mem
[
alignedDaddr
]
into the EABR register.
Syntax:
LEABR
instruction
loads
the
double-word
at
LEABR alignedDaddr
15
11 10
0
00111
alignedDaddr
Operation:
à
EABR
4
(eabr reg) mem
[
aligned addr
]
;
ó
Notes:
The value at mem
[
alignedDaddr
]
should conform to vector pointer
specification format, that is, bit positions 0 through 16 must be speci-
fied as ‘‘0’.
Accumulator is not affected.
3.4.5.5 Store Register Instructions
SXDStore X Vector Pointer
The SX instruction stores the contents of the X register into
the double-word at alignedDaddr.
Syntax:
SX alignedDaddr
15
11 10
0
01010
alignedDaddr
Operation:
à
(vector ptr) mem
[
aligned addr
] 4
X;
ó
Note:
Accumulator is not affected.
SXLDStore X Vector Pointer Lower Half
The SXL instruction stores the contents of the lower-half of
the X register into the word at mem
[
addr
]
.
Syntax:
SXL addr
15
11 10
0
11100
addr
Operation:
à
mem
[
aligned addr
] 4
X.low;
ó
Note:
Accumulator is not affected.
45
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