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| 型號(hào)： | NS32FX164V-25 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | Advanced Imaging/Communication Signal Processors |
| 中文描述： | 16-BIT, 50 MHz, MIXED DSP, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 16/102頁 |
| 文件大小： | 1053K |
| 代理商： | NS32FX164V-25 |
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2.0 Architectural Description
(Continued)
2.4.3 Instruction Set Summary
Table 2-2 presents a brief description of the NS32FX164
instruction set. The Format column refers to the Instruction
Format tables (Appendix A). The Instruction column gives
the instruction as coded in assembly language, and the De-
scription column provides a short description of the function
provided by that instruction. Further details of the exact op-
erations performed by each instruction may be found in the
Series 32000 Instruction Set Reference Manual and the
NS32CG16 Printer/Display Processor Programmer’s Refer-
ence.
Notations:
i
e
Integer length suffix: B
e
Byte
W
e
Word
D
e
Double Word
f
e
Floating Point length suffix: F
e
Standard Floating
L
e
Long Floating
gen
e
General operand. Any addressing mode can be speci-
fied.
short
e
A 4-bit value encoded within the Basic Instruction
(see Appendix A for encodings).
imm
e
Implied immediate operand. An 8-bit value appended
after any addressing extensions.
disp
e
Displacement (addressing constant): 8, 16 or 32 bits.
All three lengths legal.
reg
e
Any General Purpose Register: R0–R7.
areg
e
Any Processor Register: SP, SB, FP, INTBASE,
MOD, PSR, US (bottom 8 PSR bits).
cond
e
Any condition code, encoded as a 4-bit field within
the Basic Instruction (see Appendix A for encodings).
TABLE 2-2. NS32FX164 Instruction Set Summary
MOVES
Format
Operation
Operands
Description
4
2
7
7
7
7
7
4
MOVi
MOVQi
MOVMi
MOVZBW
MOVZiD
MOVXBW
MOVXiD
ADDR
gen,gen
short,gen
gen,gen,disp
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
Move a value.
Extend and move a signed 4-bit constant.
Move multiple: disp bytes (1 to 16).
Move with zero extension.
Move with zero extension.
Move with sign extension.
Move with sign extension.
Move effective address.
INTEGER ARITHMETIC
Format
Operation
Operands
Description
4
2
4
4
4
6
6
7
7
7
7
7
7
7
ADDi
ADDQi
ADDCi
SUBi
SUBCi
NEGi
ABSi
MULi
QUOi
REMi
DIVi
MODi
MEIi
DEIi
gen,gen
short,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
Add.
Add signed 4-bit constant.
Add with carry.
Subtract.
Subtract with carry (borrow).
Negate (2’s complement).
Take absolute value.
Multiply.
Divide, rounding toward zero.
Remainder from QUO.
Divide, rounding down.
Remainder from DIV (Modulus).
Multiply to extended integer.
Divide extended integer.
PACKED DECIMAL (BCD) ARITHMETIC
Format
Operation
Operands
Description
6
6
ADDPi
SUBPi
gen,gen
gen,gen
Add packed.
Subtract packed.
16
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