參數(shù)資料
型號: NS32FX164V-25
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 數(shù)字信號處理
英文描述: Advanced Imaging/Communication Signal Processors
中文描述: 16-BIT, 50 MHz, MIXED DSP, PQCC68
封裝: PLASTIC, LCC-68
文件頁數(shù): 69/102頁
文件大?。?/td> 1053K
代理商: NS32FX164V-25
3.0 Functional Description
(Continued)
How quickly the CPU releases the bus depends on whether
it is idle on the bus at the time the HOLD request is made,
as the CPU must always complete the current bus cycle.
Figure 3-29 shows the timing sequence when the CPU is
idle. In this case, the CPU grants the bus during the immedi-
ately following clock cycle.Figure 3-30 shows the sequence
when the CPU is using the bus at the time the HOLD re-
quest is made. If the request is made during or before the
clock cycle shown (two clock cycles before T4), the CPU
will release the bus during the clock cycle following T4. If
the request occurs closer to T4, the CPU may already have
decided to initiate another bus cycle. In that case it will not
grant the bus until after the next T4 state. Note that this
situation will also occur if the CPU is idle on the bus but has
initiated a bus cycle internally.
Note 1:
The logic value of the status pins, ST0–3, is undefined during DMA
activity.
TL/EE/11267–41
FIGURE 3-29. HOLD Timing (Bus Initially Idle)
69
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