參數(shù)資料
型號： NS32FX164V-25
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 數(shù)字信號處理
英文描述： Advanced Imaging/Communication Signal Processors
中文描述： 16-BIT, 50 MHz, MIXED DSP, PQCC68
封裝： PLASTIC, LCC-68
文件頁數(shù)： 53/102頁
文件大?。?/td> 1053K
代理商： NS32FX164V-25
3.0 Functional Description
(Continued)
Operation:
à
real X ;
integer Z ;
internal register real
internal register integer tempA;
tempX;
tempX
4
X
[
0
]
;
tempA
4
&X
[
0
]
;
for (n
4
1; n
k
LENG; n
00
)
à
if (X
[
n
]
k
tempX)
à
tempX
4
X
[
n
]
;
tempA
4
&X
[
n
]
;
ó
ó
Z
à
0
ó
4
tempA;
ó
Note:
The LENG parameter for this operation must be greater than 1.
VRFMAXDVector Real Find Maximum
The VRFMAX instruction scans the X real vector and re-
turns the address of the element with maximum value. The
resulting address is placed in Z
[
0
]
.
Syntax:
EXEC VRFMAX
15
11 10
0
10000
100 0010 0100
Operation:
à
real X;
integer Z;
internal register real tempX;
internal register integer tempA;
tempX
4
X
[
0
]
;
tempA
4
&X
[
0
]
;
for (n
4
1; n
k
LENG; n
00
)
à
if (X
[
n
]
l
tempX)
à
tempX
4
X
[
n
]
;
tempA
4
&X
[
n
]
;
ó
ó
Z
[
0
] 4
tempA;
ó
Note:
The LENG parameter for this operation must be greater than 1.
EFMAXDExtended Find Maximum
This instruction is not supported by the NS32FX161.
The EFMAX instruction implements a single iteration of
maximum search loop. The extended value in the accumula-
tor is compared with the first element of the extended Z
vector. The large value is stored back into the Z vector. In
case the larger value was the accumulator, then ss is stored
in the second location of the Z-vector (as an integer).
Syntax:
EXEC EFMAX
15
11 10
0
10000
101 0100 1011
Operation:
à
integer Y, Z
[
1
]
;
extended temp, Z
[
0
]
;
real X;
real acc A;
A
4
(real acc) ((extended)A);
temp
4
Z
[
0
]
;
if (A
l
temp)
à
temp
4
(extended) A;
Z
[
1
]
4
&X
[
0
]
;
ó
Z
[
0
] 4
temp;
ó
Note:
The Y vector must hold the following values: Y
[
0
]
must be 0x7fff, Y
[
1
]
must be 0x0001, and Y
[
2
]
must be 0x4000.
3.4.5.14 Special Instructions
ESHLDExtended Shift Left
This instruction is not supported by the NS32FX161.
The ESHL instruction performs a shift-left operation on ex-
tended-precision data in the accumulator, and stores the
more significant half of the result as a real value into the first
element of the real Z vector.
Syntax:
EXEC ESHL
15
11 10
0
10000
101 0110 0100
Operation:
à
real acc A;
A
4
(real acc) ((extended)A);
if (LENG
l
1) for (n
4
1; n
k
LENG; n
00
)
à
A
4
A
0
A;
ó
Z
[
0
] 4
(real) A;
ó
Note:
The LENG parameter for this operation must be greater than 0. When
LENG equals 1, only the real part of the accumulator is updated.
When LENG is greater than 1, both the real and the imaginary parts of
the accumulator are updated to the same value.
VCPOLYDVector Complex Polynomial
The VCPOLY instruction performs one iteration of evaluat-
ing a polynomial with real coefficients, for a vector of com-
plex-valued arguments, including down-scaling of the coeffi-
cients to avoid overflow. In addition, the instruction accumu-
lates the scaled-down energy, with a decay factor, of the
polynomial’s real coefficients.
53
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