參數(shù)資料
型號(hào)： NS32FX164V-25
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 數(shù)字信號(hào)處理
英文描述： Advanced Imaging/Communication Signal Processors
中文描述： 16-BIT, 50 MHz, MIXED DSP, PQCC68
封裝： PLASTIC, LCC-68
文件頁(yè)數(shù)： 42/102頁(yè)
文件大?。?/td> 1053K
代理商： NS32FX164V-25
3.0 Functional Description
(Continued)
accumulator. Bit 0 of the extended-precision argument is
not used during calculations. This bit is always set to ‘‘0’’
when stored back in the internal memory.
15
0
Less Significant Part
(Location 2n )
More Significant Part
(Location 2n
a
1)
Extended-precision real values are used to represent vari-
ous continuous quantities that require high accuracy. The
range of extended-precision real values is from
b
1.0 (repre-
sented as
0x80000000
) through 1.0
b
2
b
30
(represented
as
0x7FFFFFFE
).
3.4.2.6 Complex Values
Complex values are represented as pairs of real values, and
must be aligned on a double-word boundary. The less signif-
icant half represents the real part, and must be contained in
an even-numbered memory location. The more significant
half represents the imaginary part, and must be contained in
the next (odd-numbered) memory location.
15
0
Real Part
(Location 2n )
Imaginary Part
(Location 2n
a
1)
Complex values are used to represent samples of complex
baseband signals, constellation points in the complex plane,
coefficients of complex filters, and rotation angles as points
on the unit circle, etc. Both the real and imaginary parts
have the same range and accuracy as specified for real
values above.
3.4.3 Command List Format
All commands have the same fixed format, consisting of a
5-bit opcode field and a 11-bit arg field, as shown below:
15
11 10
0
opcode
arg
The opcode field specifies an operation to be performed.
The arg field interpretation is determined by the class to
which the command belongs. There are several classes of
commands, as follows:
#
Load Register Instructions
#
Store Register Instructions
#
Adjust Register Instructions
#
Flow Control Instructions
#
Internal Memory Move Instructions
#
External Memory Move Instructions
#
Arithmetic/Logical Instructions
#
Multiply-and-Accumulate Instructions
#
Multiply-and-Add Instructions
#
Clipping and Min/Max Instructions
#
Special Instructions
See Section 3.4.5 for detailed information on the DSPM in-
struction set.
3.4.4 CPU Core Interface
The interface between the DSPM and the CPU core con-
sists of the following elements:
#
Parallel Operation and Synchronization
#
CPU Core Address Space Map
#
External Memory References
3.4.4.1 Synchronization of Parallel Operation
Since the DSPM is capable of autonomous operation paral-
lel to the CPU core operation, a mechanism is needed to
synchronize the two threads of execution. The parallel syn-
chronization mechanism consists of several control and
status registers, which are used to synchronize the following
activities:
#
Initiation of the command list execution
#
Termination of the command list execution
#
Check the DSPM status
#
Access to DSPM internal RAM and registers by CPU
core instructions
#
Access to external memory by DSPM commands
The following CPU core interface control and status regis-
ters are available:
Register
Function
CLPTR
Command-List Pointer
CLSTAT
Command-List Status Register
ABORT
Abort Register
EXT
Disable External Memory References
DSPINT
Interrupt Register
DSPMASK
Mask Register
NMISTAT
NMI Status Register
Execution of the command list begins when the CPU core
writes a value into the CLPTR control register. This causes
the DSPM command-list execution unit to begin executing
commands, starting at the address written to the CLPTR
register. If the written value is outside the range of valid
RAM addresses, the result is unpredictable.
Once started, execution of the command list continues until
one of the following occurs: a HALT or a DBPT command is
executed, the CPU core writes any value into the ABORT
control register, an attempt to execute a reserved com-
mand, an attempt to access the DSPM address space while
the CLSTAT.RUN bit is ‘‘1’’ (except for accesses to the
CLSTAT, EXT, DSPINT, DSPMASK, NMISTAT, and ABORT
registers), or reset occurs. In the last case, the contents of
the DSPM internal RAM, REPEAT, and CLPTR registers are
unpredictable when execution terminates.
The CLSTAT status register can be read by CPU core in-
structions to check whether execution of the DSPM com-
mand list is active or idle. A ‘‘0’’ value read from the
CLSTAT.RUN bit indicates that execution is idle, and a ‘‘1’’
value indicates that it is active.
Whenever the execution of the command list terminates,
CLSTAT.RUN changes its value from ‘‘1’’ to ‘‘0’’, and
DSPINT.HALT is set to ‘‘1’’. The value of the DSPINT.HALT
status
bit
can
be
used
DSPMASK.HALT is set, a ‘‘1’’ value on the DSPINT.HALT
will cause the IOUT output signal to become active (low).
IOUT can be connected to an external Interrupt Controller
Unit (ICU), or directly to the INT input of the NS32FX164.
to
generate
interrupts.
If
The DSPM internal RAM and the dedicated registers, as
well as the interface control and status registers, are
mapped into certain areas of the CPU core address space
(see Section 2.2.1). Whenever execution of the DSPM com-
mand list is idle, CPU core instructions may access these
42
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