參數(shù)資料
型號(hào)： NS32FX164V-25
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 數(shù)字信號(hào)處理
英文描述： Advanced Imaging/Communication Signal Processors
中文描述： 16-BIT, 50 MHz, MIXED DSP, PQCC68
封裝： PLASTIC, LCC-68
文件頁數(shù)： 77/102頁
文件大小： 1053K
代理商： NS32FX164V-25
4.0 Device Specifications
(Continued)
4.4.2 Timing Tables
(Continued)
4.4.2.1 Output Signals: Internal Propagation Delays, NS32FX161-15, NS32FX164-20, NS32FX164-25
Symbol Figure
Description
Reference/
Conditions
NS32FX161-15
NS32FX164-20
NS32FX164-25
Units
Min
Max
Min
Max
Min
Max
t
IASa
4-6
IAS Signal Active
After R.E., CTTL T1
14
13
12
ns
t
IASia
4-6
IAS Signal Inactive
(Note 4)
After R.E., CTTL T1
0.5 t
CTp
b
6 ns
0.5 t
CTp
a
16 ns
0.5 t
CTp
b
6 ns
0.5 t
CTp
a
15 ns
0.5 t
CTp
b
6 ns
0.5 t
CTp
a
14 ns
t
IASw
4-6
IAS Pulse Width
At 0.8V (Both Edges)
20
15
10
ns
t
AIASs
4-6
AD0–AD15 Setup
Before IAS T.E.
10
10
10
ns
t
ILOa
4-14
ILO Signal Active
After R.E., CTTL
14
13
12
ns
t
ILOia
4-14
ILO Signal Inactive
After R.E., CTTL
14
13
12
ns
t
RSTOa
4-19
RSTO Signal Active
After R.E., CTTL
14
13
12
ns
t
RSTOia
4-19
RSTO Signal Inactive After R.E., CTTL
14
13
12
ns
t
RTOI
4-19
Reset to Idle
(Note 3)
After F.E. of RSTO
10
10
10
t
CTp
t
IOUTv
4-20
IOUT Signal Valid
After R.E. CTTL
14
13
12
ns
t
IOUTh
4-20
IOUT Signal Hold
After R.E. CTTL
0
0
0
ns
Note 1:
Every memory cycle starts with T4, during which Cycle Status is applied. If the CPU was idling, the sequence will be ‘‘ . . . Ti, T4, T1 . . . ’’. If the CPU was
not idling, the sequence will be ‘‘ . . . T4, T1 . . . ’’.
Note 2:
The parameters related to the ‘‘floating/not floating’’ conditions are guaranteed by characterization. Due to tester conditions, these parameters are not
100% tested.
Note 3:
Not tested, guaranteed by design.
Note 4:
Minimum values not tested, guaranteed by design.
Note 5:
When the load on AD0–15 is increased to 90 pF the value of t
ALv
is increased by no more than 5 ns. When the load on A16–23 is increased to 90 pF the
value of t
AHv
is increased by no more than 5 ns.
4.4.2.2 Input Signal Requirements: NS32FX164-15, NS32FX164-20 and NS32FX164-25
Symbol
Figure
Description
Reference/
Conditions
NS32FX164-15
NS32FX164-20
NS32FX164-25
Units
Min
Max
Min
Max
Min
Max
t
Xp
4-15
OSCIN Clock Period
R.E., OSCIN
to Next R.E, OSCIN
33
500
25
500
20
500
ns
t
Xh
4-15
OSCIN High Time
(External Clock)
At 3.5V (Both Edges)
0.5 t
Xp
b
5 ns
0.5 t
Xp
b
4 ns
0.5 t
Xp
b
3 ns
t
XI
4-15
OSCIN Low Time
At 1.0V (Both Edges)
0.5 t
Xp
b
5 ns
0.5 t
Xp
b
4 ns
0.5 t
Xp
b
3 ns
t
DIs
4-4, 4-11
Data In Setup
Before R.E., CTTL T4
15
14
10
ns
t
DIh
4-4, 4-11
Data In Hold
(Note 1)
After R.E., CTTL T4
0
0
0
ns
t
CWs
4-4, 4-5
CWAIT Signal Setup
Before R.E., CTTL
T3 or T3(w)
18
13
10
ns
t
CWh
4-4, 4-5
CWAIT Signal Hold
After R.E., CTTL
T3 or T3(w)
0
0
0
ns
t
HLDs
4-7, 4-8
HOLD Setup Time
Before R.E., CTTL
T2 or Ti
16
15
14
ns
t
HLDh
4-7, 4-8
HOLD Hold Time
After R.E., CTTL Ti
0
0
0
ns
77
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