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| 型號(hào)： | NS32FX164V-25 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | Advanced Imaging/Communication Signal Processors |
| 中文描述： | 16-BIT, 50 MHz, MIXED DSP, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 65/102頁 |
| 文件大?。?/td> | 1053K |
| 代理商： | NS32FX164V-25 |
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3.0 Functional Description
(Continued)
3.5.5.6 Special Bus Cycles
Special bus cycles are performed during CPU accesses to
the DSP Module (DSPM) registers or internal RAM. These
cycles may be used by external logic to track CPU activities
involving on-chip bus transactions.
A special bus cycle starts with the assertion of the special
output signal IAS. The ALE signal stays high during the en-
tire cycle, and the signals ADS, TSO, DBE, RD and WR are
not activated. CWAIT is ignored.
A CPU access to a DSP Module register or internal RAM
occurring while a vector operation is being executed, is de-
layed until the end of the vector operation. This delay can-
not be observed externally.
The CPU drives the data bus with the same data that is
being written into the on-chip register or RAM during a spe-
cial write cycle, and ignores the data placed on the data bus
during a special read cycle. The 24 least significant address
bits of the DSPM register being accessed are output on the
AD0–AD15 and A16–A23 signals. Figure 3-24. shows the
timing for special read and write cycles.
3.5.5.7 Slave Processor Bus Cycles
A Slave Processor bus cycle always takes exactly two clock
cycles, labeled T1 and T4 (see Figures 3-25 and 3-26 ).
During a Read cycle SPC is active from the beginning of T1
to the beginning of T4, and the data is sampled at the end of
T1. The Cycle Status pins lead the cycle by one clock peri-
od, and are sampled on the leading edge of SPC. During a
Write cycle, the CPU applies data and activates SPC at T1,
removing SPC at T4. The Slave Processor latches the
status on the leading edge of SPC and latches data on the
trailing edge.
TL/EE/11267–36
FIGURE 3-24. Special Bus Cycle Timing
65
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