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參數(shù)資料
| 型號： | NS32FX164V-25 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Advanced Imaging/Communication Signal Processors |
| 中文描述： | 16-BIT, 50 MHz, MIXED DSP, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 74/102頁 |
| 文件大?。?/td> | 1053K |
| 代理商： | NS32FX164V-25 |
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4.0 Device Specifications
(Continued)
4.2 ABSOLUTE MAXIMUM RATINGS
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Temperature under Bias
0
§
C to
a
70
§
C
b
65
§
C to
a
150
§
C
Storage Temperature
All Input or Output Voltages
with Respect to GND
b
0.5V to
a
6.5V
Note: Absolute maximum ratings indicate limits beyond
which permanent damage may occur. Continuous operation
at these limits is not intended; operation should be limited to
those conditions specified under Electrical Characteristics.
4.3 ELECTRICAL CHARACTERISTICS
T
A
e
0
§
C to
a
70
§
C, V
CC
e
5V
g
10%, GND
e
0V
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V
IH
High Level Input Voltage
2.0
V
CC
a
0.5
V
V
IL
Low Level Input Voltage
b
0.5
0.8
V
V
XL
OSCIN Input Low Voltage
0.5
V
V
XH
OSCIN Input High Voltage
3.8
V
V
RIH
RSTI High Level Input Voltage
Max
V
CC
a
0.5
V
(3.5, V
CC
b
1.5)
b
0.5
V
RIL
RSTI Low Level Input Voltage
0.7
V
V
RHYS
RSTI Hysteresis Loop Width (Note 3)
0.5
V
V
HYS
INT, NMI Hysteresis Loop Width (Note 3)
0.2
V
V
OH
High Level Output Voltage
I
OH
e b
400
m
A
I
OL
e
4 mA
V
IN
e
0.4V, SPC in Input Mode
0
s
V
IN
s
V
CC
,
All Inputs except SPC
2.4
V
V
OL
Low Level Output Voltage
0.45
V
I
ILS
SPC Input Current (Low)
1.0
mA
I
I
Input Load Current
b
20
20
m
A
I
L
Leakage Current
Output and I/O Pins in
TRI-STATE or Input Mode
0.4
s
V
OUT
s
V
CC
b
20
20
m
A
I
CC
Active Supply Current
I
OUT
e
0, T
A
e
25
§
C
(Note 2)
200
mA
Note 1:
Care should be taken by designers to provide a minimum inductance path between the GND pins and system ground in order to minimize noise.
Note 2:
I
CC
is affected by the clock scaling factor selected by the C- and M-bits in the CFG register, see Section 3.5.3.
4.4 SWITCHING CHARACTERISTICS
4.4.1 Definitions
All the timing specifications given in this section refer to
0.8V or 2.0V on the rising or falling edges of all the signals
as illustrated in Figures 4-2 and 4-3 unless specifically stat-
ed otherwise. The capacitive load is assumed to be 100 pF
on CTTL and 50 pF on all the other output signals.
TL/EE/11267–44
FIGURE 4-2. Output Signals Specification Standard
Abbreviations:
L.E.D Leading Edge
T.E.D Traling Edge
R.E.D Rising Edge
F.E.D Falling Edge
TL/EE/11267–45
FIGURE 4-3a. Input Signals Specification Standard
TL/EE/11267–71
FIGURE 4-3b. RSTI, INT, NMI Hysteresis
74
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