參數資料
型號: NS32FX164V-25
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 數字信號處理
英文描述: Advanced Imaging/Communication Signal Processors
中文描述: 16-BIT, 50 MHz, MIXED DSP, PQCC68
封裝: PLASTIC, LCC-68
文件頁數: 64/102頁
文件大小: 1053K
代理商: NS32FX164V-25
3.0 Functional Description
(Continued)
3.5.5.5 Interrupt Control Cycles
Activating the INT or NMI pin on the CPU will initiate one or
more bus cycles whose purpose in interrupt control rather
than the tranfer of instructions or data. Execution of the
Return from Interrupt Instruction (RETI) will also cause In-
terrupt Control bus cycles. These differ from instruction or
data transfers only in the status presented on pins ST0–
ST3. All Interrupt Control cycles are single-byte Read cy-
cles.
Table 3-4 shows the Interrupt Control sequences associat-
ed with each interrupt and with the return from its service
routine. For full details of the NS32FX164 interrupt struc-
ture, see Section 3.2.
TABLE 3-4. Interrupt Sequences
Cycle
Status
Address
DDIN
HBE
A0
High Bus
Low Bus
A. Non-Maskable Interrupt Control Sequence
Interrupt Acknowledge
1
0100
FFFF00
16
0
1
0
Don’t Care
Don’t Care
Interrupt Return
None: Performed through Return from Trap (RETT) instruction.
B. Non-Vectored Interrupt Control Sequence
Interrupt Acknowledge
1
0100
FFFE00
16
0
1
0
Don’t Care
Don’t Care
Interrupt Return
None: Performed through Return from Trap (RETT) instruction.
C. Vectored Interrupt Sequence: Non-Cascaded
Interrupt Acknowledge
1
0100
FFFE00
16
0
1
0
Don’t Care
Vector:
Range: 0–127
Interrupt Return
1
0110
FFFE00
16
0
1
0
Don’t Care
Vector: Same as
in Previous Int.
Ack. Cycle
D. Vectored Interrupt Sequence: Cascaded
Interrupt Acknowledge
1
0100
FFFE00
16
0
1
0
Don’t Care
Cascade Index:
range
b
16 to
b
1
(The CPU here uses the Cascade Index to find the Cascade Address.)
2
0101
Cascade
Address
0
1 or
0
*
0 or
1
*
Vector, range 0–255; on appropriate
half or Data Bus for even/odd
address
Interrupt Return
1
0110
FFFE00
16
0
1
0
Don’t Care
Cascade Index:
same as in
previous Int.
Ack. Cycle
(The CPU here uses the Cascade Index to find the Cascade Address.)
2
0111
Cascade
Address
0
1 or
0
*
0 or
1
*
Don’t Care
Don’t Care
*
If the Cascaded ICU Address is Even (A0 is low), then the CPU applies HBE high and reads the vector number from bits 0–7 of the Data Bus.
If the address is Odd (A0 is high), then the CPU applies HBE low and reads the vector number from bits 8–15 of the Data Bus. The vector number may be in the
range 0–225.
64
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