參數(shù)資料
型號(hào)： NS32FX164V-25
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 數(shù)字信號(hào)處理
英文描述： Advanced Imaging/Communication Signal Processors
中文描述： 16-BIT, 50 MHz, MIXED DSP, PQCC68
封裝： PLASTIC, LCC-68
文件頁(yè)數(shù)： 57/102頁(yè)
文件大小： 1053K
代理商： NS32FX164V-25
3.0 Functional Description
(Continued)
TABLE 3-3. External Oscillator
Specifications Crystal Characteristics
Type
AT-Cut
Tolerance
0.005% at
a
25
§
C
0.01% from 0
§
C to
a
70
§
C
Stability
Resonance
30 MHz:
40 MHz or 50 MHz:
Fundamental (Parallel)
Third Overtone (Parallel)
Maximum Series Resistance
50
X
7 pF
Maximum Shunt Capacitance
R, C and L Values
Frequency
(MHz)
R1
(k
X
)
R2
(
X
)
C1
(pF)
C2
(pF)
C3
(pF)
L
(
m
H)
30
30
40
50
180
180
150
150
51
51
51
51
20
20
20
20
20
20
20
20
800–1300
800–1300
800–1300
3.3
1.8
1.1
3.5.3 Power Save Mode
The NS32FX164 provides a power save feature that can be
used to significantly reduce the power consumption at times
when the computational demand decreases. The device
uses the clock signal at the OSCIN pin to derive the internal
clock as well as the external signals CTTL and FCLK. The
frequency of these clock signals is affected by the clock
scaling factor. Scaling factors of 1, 2, 4, or 8 can be select-
ed by properly setting the C- and M-bits in the CFG register.
The power save mode should not be used to reduce the
clock frequency below the minimum frequency required by
the CPU.
Upon reset, both C and M are set to zero, thus maximum
clock rate is selected.
Due to the fact that the C- and M-bits are programmed by
the SETCFG instruction, the power save feature can only be
controlled by programs running in supervisor mode.
The following table shows the C- and M-bit settings for the
various scaling factors, and the resulting supply current for a
crystal frequency of 50 MHz.
Clock Scaling Factor vs Supply Current
C
M
Scaling
Factor
CPU Clock
Frequency
Typical I
CC
at
a
5V
0
0
1
1
0
1
0
1
1
2
4
8
25 MHz
12.5 MHz
6.25 MHz
3.13 MHz
200 mA
120 mA
80 mA
55 mA
3.5.4 Resetting
The RSTI input pin is used to reset the NS32FX164. The
CPU samples RSTI on the falling edge of CTTL.
Whenever a low level is detected, the CPU responds imme-
diately. Any instruction being executed is terminated; any
results that have not yet been written to memory are dis-
carded; and any pending interrupts and traps are eliminated.
The internal latch for the edge-sensitive NMI signal is
cleared. The DSP module ST register is set to 0.
On application of power, RSTI must be held low for at least
50
m
s after V
CC
is stable. This is to ensure that all on-chip
voltages are completely stable before operation. Whenever
a Reset is applied, it must also remain active for not less
than 64 CTTL cycles. See Figures 3-18 and 3-19.
TL/EE/11267–30
FIGURE 3-18. Power-On Reset Requirements
TL/EE/11267–31
FIGURE 3-19. General Reset Timing
While in the Reset state, the CPU drives the signals ADS,
IAS, RD, WR, DBE, TSO, BPU, IOUT and DDIN inactive.
AD0–AD15, A16–A23 and SPC are floated, ALE is HIGH
and the state of all other output signals is undefined.
The internal CPU clock and CTTL run at half the frequency
of the signal on the OSCIN pin.
The HOLD signal must be kept inactive. After the RSTI sig-
nal is driven high, the CPU will stay in the reset condition for
approximately 8 clock cycles and then it will begin execution
at address 0.
The PSR is reset to 0. The CFG C- and M-bits are reset to 0.
FCLK runs at the same frequency as OSCIN. NMI is en-
abled to allow Non-Maskable Interrupts. The following con-
ditions are present after reset due to the PSR being reset to
0:
Tracing is disabled.
Supervisor mode is enabled.
Supervisor stack space is used when the TOS addressing
mode is indicated.
No trace traps are pending.
Only NMI is enabled. Maskable interrupts are disabled.
BPU is inactive high.
The Clock Scaling Factor is set to 1, refer to Section 3.5.3.
Note that vector/non-vectored interrupts have not been se-
lected. While interrupts are disabled, a SETCFG
[
I
]
instruc-
tion must be executed to enable vectored interrupts. If non-
vectored interrupts are required, a SETCFG without the
[
I
]
must be executed.
The presence/absence of the NS32081, NS32181, or
NS32381 has also not been declared. If there is a Floating-
Point Unit, a SETCFG
[
F
]
instruction must be executed. If
there is no floating-point unit, a SETCFG without the
[
F
]
must be executed.
57
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