Memory Controller
15-44
MPC823 USER’S MANUAL
MOTOROLA
MEMORY
CONTROLLER
15
15.5.1.4 EXCEPTION REQUESTS. When an access to a memory device is initiated by the
MPC823 under UPM control, the external device may assert the TEA, SRESET, or HRESET
signal. The UPM provides a mechanism that allows you to handle the memory control
signals to meet the timing requirements of the device and assume no data is lost.
15.5.2 Programming the User-Programmable Machine
The user-programmable machine is a micro-sequencer that requires micro-instructions or
RAM words to generate signal timings for different memory cycles. You should program the
user-programmable machine in the following order:
1. Write a program into the RAM array.
2. Set up the base and option registers.
3. Program the memory periodic timer prescaler register.
4. Program the machine mode register.
Each user-programmable machine has a machine mode register (MxMR) that defines the
general attributes for operation. The PTA field of the MAMR and the PTB field of the MBMR
defines the period for the timers associated with UPMA and UPMB. If the PTAE bit is set,
the periodic timer of UPMA requests a transaction when the timer period expires. If the
PTBE bit is set, the periodic timer of UPMB requests a transaction when the timer period
expires.
To initiate a software request, issue the appropriate command to the memory command
register with the MAD field indexing the first entry of the UPM entry word. Command
execution is accomplished by accessing consecutive RAM words (one per clock) until the
word with the LAST bit set is encountered. The words read from the RAM provide
information about the value and timing of the external signals controlled by the UPM and
about specific strobes that control internal memory controller resources.
There is a disable timer mechanism associated with each user-programmable machine that
is only active between memory accesses. This timer is used to provide a delay between
successive memory cycles to the same bank.
Each of the UPMs can control how the address of the current access is output to the external
pins. Address multiplexing configurations for a specific memory or device can be selected
in the machine mode register. There is also a multiplexing field in the RAM word that is used
to control cycle-by-cycle accesses. Specific user-programmable machine register