
Communication Processor Module
16-78
MPC823 USER’S MANUAL
MOTOROLA
TIMERS
COMMUNICATION
16
PROCESSOR
MODULE
Restart gate mode performs the same function as normal mode, except it also resets the
counter on the falling edge of the TGATE1 pin. This mode can be used in pulse interval
measurement and bus monitoring applications:
Pulse Measurement—The restart gate mode can measure a low pulse on the TGATE1
pin. The rising edge of the TGATE1 pin completes the measurement and if TGATE1 is
externally connected to TINx, it causes the timer to capture the count value and
generate a rising-edge interrupt.
Bus Monitoring—The restart gate mode can detect a signal that is abnormally stuck low.
The bus signal should be connected to the TGATE1 pin. The timer count is reset on the
falling edge of the bus signal and if the bus signal does not go high again within the
number of user-defined clocks, an interrupt can be generated.
The gate function is enabled in the timer mode register and the gate operating mode is
selected in the timer global configuration register.
16.4.2.1 CASCADED MODE. In this mode, the 16-bit timers can be internally cascaded
into a 32-bit counter. Since the decision to cascade timers is made independently, you have
the option of selecting four 16-bit timers or two 32-bit timers. The timer global configuration
register is used to put the timers into cascaded mode. See
Figure 16-35 for details.
If the CAS2 bit is set in the timer global configuration register, the two timers function as a
32-bit timer with a 32-bit timer reference register, timer capture register, and timer counter.
In this case, timers 1 and 3 are ignored and timers 2 and 4 should be used to define the
mode. The capture is controlled by the TIN2 pin and the interrupts are generated by the
TER2 pin. When operating in cascaded mode, the cascaded timer reference register, timer
capture register, and timer counter should always be referenced with 32-bit bus cycles.
Note: TGATE1 is internally synchronized to the timebase clock (TMBCLK). If it meets
the asynchronous input setup time, then (when working with the internal clock)
the counter begins counting after one system clock.
Figure 16-35. Timer Cascaded Mode Block Diagram
TIMER3
TIMER4
CAPTURE
CLOCK
TRR, TCR, TCN CONNECTED TO DATA BUS
PINS 31-16.
PINS 15-0.
TIMER1
TIMER2
CLOCK
CAPTURE
TRR, TCR, TCN CONNECTED TO DATA BUS
PINS 31-16.
PINS 15-0.