
Communication Processor Module
MOTOROLA
MPC823 USER’S MANUAL
16-237
SCC2
COMMUNICATION
16
PROCESSOR
MODULE
DRT—Disable Receiver While Transmitting
0 = Normal operation.
1 = While data is being transmitted by the serial communication controller, the receiver
is disabled. This configuration is useful if the HDLC channel is configured onto a
multidrop line and you do not want to receive your own transmission.
BUS—HDLC Bus Mode
0 = Normal HDLC operation.
BRM—HDLC Bus RTS Mode
This bit is only valid if BUS = 1. Otherwise, it is ignored.
0 = Normal RTS operation during HDLC bus mode. RTS is asserted on the first bit of
the transmit frame and negated after the first collision bit is received.
1 = Special RTS operation during HDLC bus mode. RTS is delayed by one bit with
respect to the normal case. This is useful when the HDLC bus protocol is being run
locally and transmitted over a long-distance transmission line at the same time.
Data can be delayed one bit before it is sent over the transmission line, thus RTS
can be used to enable the transmission line buffers. The result is a clean signal
level sent over the transmission line.
MFF—Multiple Frames in FIFO
0 = Normal operation. The transmit FIFO must never contain more than one HDLC
frame. The CTS lost status is reported accurately on a per-frame basis. The
receiver is not affected by this bit.
1 = The transmit FIFO can contain multiple frames, but lost CTS is not guaranteed to
be reported on the exact buffer/frame it truly occurred on. This option, however,
can improve the performance of HDLC transmissions of small back-to-back frames
or in cases where you prefer to limit the number of flags transmitted between
frames. The receiver is not affected by this bit.
16.9.16.9 SCC2 HDLC RECEIVE BUFFER DESCRIPTOR.The SCC2 HDLC controller
uses the receive (RX) buffer descriptor to report information about the data received for each
buffer. An example of the RX buffer descriptor process is illustrated in
Figure 16-78.Note:
The communication processor module sets all the status bits in this buffer
descriptor. You should clear all the status bits before submitting the buffer
descriptor to the communication processor module. For example, the parity error
bit is only set when a parity error occurs.