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Communication Processor Module
16-466
MPC823 USER’S MANUAL
MOTOROLA
I 2
C
COMMUNICATION
16
PROCESSOR
MODULE
16.13.7.8 I2C MASK REGISTER. The 8-bit read/write I2C mask register (I2CMR) has the
same bit formats as the I2CER. If a bit in the I2CMR is 1, the corresponding interrupt in the
I2CER is enabled. If the bit is zero, the corresponding interrupt in the I2CER is masked. This
register is cleared by reset.
16.13.8 I2C Controller Initialization Sequence
The following initialization sequence is for the I2C controller to operate in master mode, and
read one byte from a slave device that contains an internal read address. The I2C controller
operates the SCL at 391kHz. A system frequency of 50MHz is assumed. The SDA and SCL
pins of the MPC823 are connected to an external 5V power supply with 6.8K Ohm to 10K
Ohm resistors.
1. Configure the port B pins to enable the SDA and SCL pins. Write PBPAR, PBDIR, and
PBODR bits 26 and 27 with ones.
2. Disable the I2C controller by clearing the I2MOD register, including the EN bit. Now
you can modify other fields in the I2MOD register.
3. Configure the I2C dedicated baud rate generator to operate at 391kHz at a system
frequency of 50MHz by programming the divider and pre-divider. The overall I2C baud
rate generator clock divider is 128 (decimal), and is realized by establishing a
pre-divider of 8 and a divider of 16. Write the PDIV field of the I2MOD register with 2
to pre-divide by 8. Write the DIV field of the I2BRG register with 5 to divide by 16.
4. Write 0x01 to the I2COM register to configure controller for master mode operation.
5. Write 0x0001 to the SDCR to set the SDMA bus arbitration level to 5.
6. Write RBASE and TBASE in the I2C parameter RAM to point to the RX and TX buffer
descriptors in the dual-port RAM. Assuming the initial RX buffer descriptor at the
beginning of dual-port RAM and the initial TX buffer descriptor 64 bytes from the
beginning, write RBASE with 0x2000 and TBASE with 0x2040.
7. Write 0x11 into the CPCR to execute the INIT RX AND TX PARAMS command for I2C.
8. Write 0x15 into the RFCR and TFCR for normal operation.
9. Write MRBLR with the maximum bytes per receive buffer. For this case, assume 16
bytes, so MRBLR = 0x10.
10. Initialize the RX buffer descriptor. Assume the RX data buffer is at 0x00001000 in main
memory. Write 0xB000 to RX_BD_Status, 0x0 to RX_BD_Length (optional), and
0x00001000 to RX_BD_Pointer.
I2CMR
BIT
0
1
2
3
4
5
6
7
FIELD
RESERVED
TXE
RESERVED
BSY
TXB
RXB
RESET
0
00000
R/W
R/W
ADDR
(IMMR & 0xFFFF0000) + 0x874