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Communication Processor Module
MOTOROLA
MPC823 USER’S MANUAL
16-163
SCC2
COMMUNICATION
16
PROCESSOR
MODULE
CTSS—CTS Sampling
0 = The CTS signal is assumed to be asynchronous with the data. It is internally
synchronized by the serial communication controller and data is then transmitted
after several serial clock delays.
1 = The CTS signal is assumed to be synchronous with the data, which speeds up
operation. In this mode, CTS must transition while the transmit clock is in the low
state. As soon as CTS is low, data immediately begins transmission. This mode is
especially useful when connecting an MPC823 in transparent mode since it allows
the RTS signal of one MPC823 to be directly connected to the CTS signal of
another MPC823.
TFL—Transmit FIFO Length
0 = Normal operation. The transmit FIFO is 32 bytes for the serial communication
controller.
1 = The transmit FIFO is 1 byte and can be used with character-oriented protocols to
ensure a minimum FIFO latency at the expense of performance.
RFW—Receive FIFO Width
0 = Receive FIFO is 32 bits wide for maximum performance. Data is not normally
written to receive buffers until at least 32 bits are received. This configuration is
required for HDLC-type protocols and Ethernet, but it is recommended for
high-performance transparent modes. In this mode, the receive FIFO is 32 bytes
for the serial communication controller.
1 = Low-latency operation. The receive FIFO is 8 bits wide and the receive FIFO is a
quarter its normal size (8 bytes). This allows data to be written to the data buffer
when a character is received, instead of waiting to receive 32 bits. This
configuration must be chosen for character-oriented protocols, such as UART. It
can also be used for low-performance, low-latency, transparent operation, if
preferred. However, it must not be used with HDLC, HDLC Bus, AppleTalk, or
Ethernet because it will cause erratic behavior to occur.
TXSY—Transmitter Synchronized to the Receiver
This bit is specifically intended for X.21 applications where the transmitted data must begin
an exact multiple of 8-bit periods after the received data arrives.
0 = No synchronization between receiver and transmitter (default).
1 = The transmit bitstream is synchronized to the receiver. Additionally, if RSYN = 1,
then transmission in the totally transparent mode does not occur until the receiver
has synchronized with the bitstream and the CTS signal is asserted to the serial
communication controller. Assuming CTS is already asserted, transmission begins
eight clocks after the receiver starts receiving data.